Añade testbench para fetch y decode

2 files changed, 30 insertions, 3 deletions

diff --git a/rtl/top/decode_test.sv b/rtl/top/decode_test.sv
index f701aff..6aa2159 100644
--- a/rtl/top/decode_test.sv
+++ b/rtl/top/decode_test.sv
@@ -1,9 +1,11 @@
 `timescale 1 ns / 1 ps
+`include "core/decode/isa.sv"
+`include "core/uarch.sv"
 
 module decode_test
 (
     input  word            insn,
-	input  logic           n, z, c, v
+	input  logic           n, z, c, v,
 
 	output datapath_decode ctrl,
 	output psr_decode      psr_ctrl,
@@ -15,8 +17,8 @@ module decode_test
 	output coproc_decode   coproc_ctrl
 
 );
-    psr_flags nzcv;
-	assign {n, z, c, v} = nzcv;
+    psr_flags flags;
+	assign flags = {n, z, c, v};
 
     core_decode DUT (.*);
 
diff --git a/rtl/top/fetch_test.sv b/rtl/top/fetch_test.sv
new file mode 100644
index 0000000..bdfa2c5
--- /dev/null
+++ b/rtl/top/fetch_test.sv
@@ -0,0 +1,25 @@
+`timescale 1 ns / 1 ps
+`include "core/uarch.sv"
+
+module fetch_test
+(
+    input  logic clk,
+	             stall,
+	             branch,
+	             flush,
+	             fetched,
+	             wr_pc,
+	input  ptr   branch_target,
+	input  word  wr_current,
+	             fetch_data,
+
+	output logic fetch,
+	output word  insn,
+	output ptr   insn_pc,
+	             addr
+
+);
+
+    core_fetch #(.PREFETCH_ORDER(3)) DUT (.*);
+
+endmodule
\ No newline at end of file