diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-09-30 00:07:20 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-09-30 01:20:48 -0600 |
| commit | d1b10aa380578b5af20081dd37f2d36ec111cbd2 (patch) | |
| tree | e28ea62a6d95514e0a89e4fa8dd88eb9f37b73c1 /rtl/smp/pe.sv | |
| parent | 1c9c08d72f32265501f1f14ad8a0d1e0b2b8850f (diff) | |
platform: implement SMP controller
Diffstat (limited to 'rtl/smp/pe.sv')
| -rw-r--r-- | rtl/smp/pe.sv | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/rtl/smp/pe.sv b/rtl/smp/pe.sv new file mode 100644 index 0000000..f50ed2f --- /dev/null +++ b/rtl/smp/pe.sv @@ -0,0 +1,47 @@ +module mp_pe +#(parameter IS_BSP=0) +( + input logic clk, + rst_n, + + input logic write, + input logic[7:0] writedata, + output logic[7:0] readdata, + + input logic cpu_halted, + breakpoint, + + output logic halt, + step +); + + struct packed + { + logic step, halt, run; + } req; + + struct packed + { + logic breakpoint, cpu_halted; + } status; + + assign req = writedata[$bits(req) - 1:0]; + assign readdata = {{(8 - $bits(status)){1'b0}}, status}; + + always @(posedge clk or negedge rst_n) + if (!rst_n) begin + halt <= IS_BSP ? 0 : 1; // Boot es single-core + step <= 0; + status <= {($bits(status)){1'b0}}; + end else begin + status.breakpoint <= breakpoint; + status.cpu_halted <= cpu_halted; + + //Se hace halt hasta el siguiente ciclo después de que se + //solicita el breakpoint + step <= !breakpoint || (req.step && write); + halt <= (halt || breakpoint || (req.halt && write)) + && !((req.run || req.step) && write); + end + +endmodule |
