rtl: fix quartus errors: parser, synthesis, fitter

12 files changed, 141 insertions, 120 deletions

diff --git a/rtl/gfx/gfx_ctz.sv b/rtl/gfx/gfx_ctz.sv
index 2713f8a..f1075d7 100644
--- a/rtl/gfx/gfx_ctz.sv
+++ b/rtl/gfx/gfx_ctz.sv
@@ -8,11 +8,17 @@ module gfx_ctz
 	output logic[$clog2(WIDTH):0] ctz
 );
 
+	logic[WIDTH - 1:0] value_rev;
+
 	gfx_clz #(WIDTH) clz
 	(
 		.clk,
-		.value({<<{value}}),
+		.value(value_rev),
 		.clz(ctz)
 	);
 
+	always_comb
+		for (int i = 0; i < $bits(value); ++i)
+			value_rev[i] = value[$bits(value) - i - 1];
+
 endmodule
diff --git a/rtl/gfx/gfx_front_back.sv b/rtl/gfx/gfx_front_back.sv
index b768532..6618353 100644
--- a/rtl/gfx/gfx_front_back.sv
+++ b/rtl/gfx/gfx_front_back.sv
@@ -1,5 +1,6 @@
-interface gfx_front_back
-import gfx::*;;
+interface gfx_front_back;
+
+	import gfx::*;
 
 	struct
 	{
diff --git a/rtl/gfx/gfx_isa.sv b/rtl/gfx/gfx_isa.sv
index 7239478..cc34156 100644
--- a/rtl/gfx/gfx_isa.sv
+++ b/rtl/gfx/gfx_isa.sv
@@ -5,80 +5,86 @@ package gfx_isa;
 
 	typedef logic signed[7:0] pc_offset;
 
-	typedef union packed
+	typedef struct packed
 	{
 		sgpr_num sgpr;
-
-		struct packed
-		{
-			logic[$bits(sgpr_num) - $bits(vgpr_num) - 1:0] reserved;
-			vgpr_num                                       num;
-		} vgpr;
-	} xgpr_num;
+	} xgpr_sgpr;
 
 	typedef struct packed
 	{
-		enum logic[1:0]
-		{
-			REGS_SVS = 2'b00,
-			REGS_SSS = 2'b01,
-			REGS_VVS = 2'b10,
-			REGS_VVV = 2'b11
-		} reg_mode;
+		logic[$bits(sgpr_num) - $bits(vgpr_num) - 1:0] reserved;
+		vgpr_num                                       vgpr;
+	} xgpr_vgpr;
 
-		union packed
-		{
-			struct packed
-			{
-				logic b_is_imm;
+	typedef xgpr_vgpr xgpr_num;
 
-				union packed
-				{
-					logic[12:0] imm;
+	typedef enum logic[1:0]
+	{
+		REGS_SVS = 2'b00,
+		REGS_SSS = 2'b01,
+		REGS_VVS = 2'b10,
+		REGS_VVV = 2'b11
+	} xgpr_mode;
 
-					struct packed
-					{
-						logic      from_consts;
-						logic[7:0] reserved;
-						xgpr_num   r;
-					} read;
-				} b;
+	typedef struct packed
+	{
+		logic[12:0] imm;
+	} dst_src_rr_b_imm;
 
-				xgpr_num ra,
-				         rd;
-			} rr;
-		} dst_src;
+	typedef struct packed
+	{
+		logic      from_consts;
+		logic[7:0] reserved;
+		xgpr_num   r;
+	} dst_src_rr_b_read;
 
-		logic reg_rev;
+	typedef struct packed
+	{
+		logic             b_is_imm;
+		dst_src_rr_b_read b;
+		xgpr_num          ra,
+		                  rd;
+	} dst_src_rr;
 
-		union packed
-		{
-			struct packed
-			{
-				enum logic[4:0]
-				{
-					INSN_FPINT_MOV  = 0,
-					INSN_FPINT_FMUL = 1,
-					INSN_FPINT_IMUL = 2,
-					INSN_FPINT_FADD = 3,
-					INSN_FPINT_RES4 = 4,
-					INSN_FPINT_FMAX = 5,
-					INSN_FPINT_RES6 = 6,
-					INSN_FPINT_FMIN = 7,
-					INSN_FPINT_RES8 = 8,
-					INSN_FPINT_FCVT = 9,
-					INSN_FPINT_RES[10:31]
-				} op;
-			} fpint;
-		} by_class;
+	typedef enum logic[1:0]
+	{
+		INSN_FPINT = 2'd0,
+		INSN_MEM   = 2'd1,
+		INSN_SFU   = 2'd2,
+		INSN_GROUP = 2'd3
+	} insn_class;
+
+	typedef enum logic[4:0]
+	{
+		INSN_FPINT_MOV  = 5'd0,
+		INSN_FPINT_FMUL = 5'd1,
+		INSN_FPINT_IMUL = 5'd2,
+		INSN_FPINT_FADD = 5'd3,
+		INSN_FPINT_RES4 = 5'd4,
+		INSN_FPINT_FMAX = 5'd5,
+		INSN_FPINT_RES6 = 5'd6,
+		INSN_FPINT_FMIN = 5'd7,
+		INSN_FPINT_RES8 = 5'd8,
+		INSN_FPINT_FCVT = 5'd9,
+		INSN_FPINT_RES[10:31]
+	} insn_fpint_op;
+
+	typedef struct packed
+	{
+		xgpr_mode     reg_mode;
+		dst_src_rr    dst_src;
+		logic         reg_rev;
+		insn_fpint_op op;
+		insn_class    op_class;
+	} insn_fpint;
 
-		enum logic[1:0]
-		{
-			INSN_FPINT = 0,
-			INSN_MEM   = 1,
-			INSN_SFU   = 2,
-			INSN_GROUP = 3
-		} insn_class;
-	} insn_word;
+	typedef struct packed
+	{
+		xgpr_mode   reg_mode;
+		dst_src_rr  dst_src;
+		logic       reg_rev;
+		logic[4:0]  op_data;
+		insn_class  op_class;
+	} insn_any;
 
 endpackage
diff --git a/rtl/gfx/gfx_sched.sv b/rtl/gfx/gfx_sched.sv
index 03498e4..dd6ca91 100644
--- a/rtl/gfx/gfx_sched.sv
+++ b/rtl/gfx/gfx_sched.sv
@@ -15,7 +15,6 @@ import gfx::*;
 	logic axi_ready, axi_valid, bram_ready, bram_read, bram_write, bram_write_next,
 	      mem_instr, mem_la_read, mem_la_write, mem_ready, mem_valid, select_bram;
 
-	word bram[SCHED_BRAM_WORDS];
 	word axi_rdata, bram_rdata, mem_addr, mem_la_addr, mem_rdata, mem_wdata;
 	logic[$bits(word) / $bits(byte) - 1:0] mem_wstrb;
 
@@ -113,17 +112,18 @@ import gfx::*;
 		.mem_rdata(axi_rdata)
 	);
 
-	always_ff @(posedge clk) begin
-		if (bram_write) begin
-			for (int i = 0; i < $bits(mem_wstrb); ++i)
-				if (mem_wstrb[i])
-					bram[bram_addr][i] <= mem_wdata[i];
-
-			bram_rdata <= 'x;
-		end else
-			bram_rdata <= bram[bram_addr];
-	end
+	genvar i;
+	generate
+		for (i = 0; i < BYTES_PER_WORD; ++i) begin: byte_lanes
+			logic[7:0] bram[SCHED_BRAM_WORDS];
 
+			always_ff @(posedge clk) begin
+				bram_rdata[8 * i +: 8] <= bram[bram_addr];
+				if (bram_write & mem_wstrb[i])
+					bram[bram_addr] <= mem_wdata[8 * i +: 8];
+			end
+		end
+	endgenerate
 
 	always_ff @(posedge clk or negedge rst_n)
 		if (~rst_n) begin
diff --git a/rtl/gfx/gfx_shader.sv b/rtl/gfx/gfx_shader.sv
index 6b81b41..8ff6edc 100644
--- a/rtl/gfx/gfx_shader.sv
+++ b/rtl/gfx/gfx_shader.sv
@@ -1,6 +1,5 @@
 module gfx_shader
-import gfx::*;
-import gfx_shader_schedif_pkg::*;
+import gfx::*, gfx_shader_schedif_pkg::*;
 (
 	input  logic     clk,
 	                 rst_n,
diff --git a/rtl/gfx/gfx_shader_back.sv b/rtl/gfx/gfx_shader_back.sv
index 968a34b..f7c2349 100644
--- a/rtl/gfx/gfx_shader_back.sv
+++ b/rtl/gfx/gfx_shader_back.sv
@@ -159,7 +159,7 @@ module gfx_shader_writeback_arbiter4
 		.clk,
 		.rst_n,
 		.a(p0_p1.rx),
-		.b(p2_p3.tx),
+		.b(p2_p3.rx),
 		.out
 	);
 
@@ -267,12 +267,12 @@ import gfx::*;
 		end
 
 		regs.sgpr_write.data = setup.write.gpr_value;
-		regs.sgpr_write.sgpr = setup.write.gpr.sgpr;
+		regs.sgpr_write.sgpr = setup.write.gpr;
 		regs.sgpr_write.group = setup.write.group;
 
 		if (scalar_wb) begin
 			regs.sgpr_write.data = wb.lanes[0];
-			regs.sgpr_write.sgpr = wb.dest.sgpr;
+			regs.sgpr_write.sgpr = wb.dest;
 			regs.sgpr_write.group = wb.group;
 		end
 
@@ -291,7 +291,7 @@ import gfx::*;
 			loop_hold[i] = loop_hold[i - 1];
 
 		loop_hold[0].mask = wb.mask;
-		loop_hold[0].vgpr = wb.dest.vgpr.num;
+		loop_hold[0].vgpr = wb.dest.vgpr;
 		loop_hold[0].group = wb.group;
 		loop_hold[0].pc_add = wb.pc_add;
 		loop_hold[0].pc_update = wb.pc_update;
diff --git a/rtl/gfx/gfx_shader_front.sv b/rtl/gfx/gfx_shader_front.sv
index 3398e52..acdde78 100644
--- a/rtl/gfx/gfx_shader_front.sv
+++ b/rtl/gfx/gfx_shader_front.sv
@@ -1,9 +1,9 @@
 typedef struct
 {
-	logic              valid,
-	                   retry;
-	gfx::group_id      group;
-	gfx_isa::insn_word insn;
+	logic             valid,
+	                  retry;
+	gfx::group_id     group;
+	gfx_isa::insn_any insn;
 } front_wave;
 
 typedef struct
@@ -124,7 +124,7 @@ import gfx::*;
 
 	assign mem.arid = '0;
 	assign mem.arlen = ($bits(mem.arlen))'($bits(oword) / $bits(word) - 1);
-	assign mem.arsize = 3'b101; // 32 bits/beat
+	assign mem.arsize = 3'b010; // 4 bytes/beat
 	assign mem.araddr = {araddr, ($clog2($bits(oword)) - $clog2($bits(word)) + SUBWORD_BITS)'('0)};
 	assign mem.arburst = 2'b01; // Incremental mode
 
@@ -424,17 +424,16 @@ import gfx::*;
 		insn_valid <= valid_5;
 
 		if (fetch_ready & fetch_valid) begin
-			fetch_shift[0] <= fetch_data;
-			for (int i = 1; i < $size(fetch_shift); ++i)
-				fetch_shift[i] <= fetch_shift[i - 1];
+			fetch_shift[$size(fetch_shift) - 1] <= fetch_data;
+			for (int i = 0; i < $size(fetch_shift) - 1; ++i)
+				fetch_shift[i] <= fetch_shift[i + 1];
 		end
 	end
 
 endmodule
 
 module gfx_shader_read_regs
-import gfx::*;
-import gfx_isa::*;
+import gfx::*, gfx_isa::*;
 (
 	input  logic               clk,
 	                           rst_n,
@@ -470,7 +469,7 @@ import gfx_isa::*;
 		for (int i = 1; i < $size(out_hold); ++i)
 			out_hold[i] <= out_hold[i - 1];
 
-		passthru_hold[0].dest <= in.insn.dst_src.rr.rd;
+		passthru_hold[0].dest <= in.insn.dst_src.rd;
 		unique case (in.insn.reg_mode)
 			REGS_SVS, REGS_SSS:
 				passthru_hold[0].dest_scalar <= 1;
@@ -484,13 +483,13 @@ import gfx_isa::*;
 
 		read.op.group <= in.group;
 
-		read.op.b_imm <= in.insn.dst_src.rr.b.imm;
-		read.op.a_sgpr <= in.insn.dst_src.rr.ra.sgpr;
-		read.op.b_sgpr <= in.insn.dst_src.rr.b.read.r.sgpr;
-		read.op.a_vgpr <= in.insn.dst_src.rr.ra.vgpr.num;
-		read.op.b_vgpr <= in.insn.dst_src.rr.b.read.r.vgpr.num;
-		read.op.b_is_imm <= in.insn.dst_src.rr.b_is_imm;
-		read.op.b_is_const <= in.insn.dst_src.rr.b.read.from_consts;
+		read.op.b_imm <= in.insn.dst_src.b;
+		read.op.a_sgpr <= in.insn.dst_src.ra;
+		read.op.b_sgpr <= in.insn.dst_src.b.r;
+		read.op.a_vgpr <= in.insn.dst_src.ra.vgpr;
+		read.op.b_vgpr <= in.insn.dst_src.b.r.vgpr;
+		read.op.b_is_imm <= in.insn.dst_src.b_is_imm;
+		read.op.b_is_const <= in.insn.dst_src.b.from_consts;
 		read.op.scalar_rev <= reg_rev;
 
 		unique case (in.insn.reg_mode)
@@ -525,8 +524,7 @@ import gfx_isa::*;
 endmodule
 
 module gfx_shader_decode_class
-import gfx::*;
-import gfx_isa::*;
+import gfx::*, gfx_isa::*;
 (
 	input  logic           clk,
 	                       rst_n,
@@ -573,7 +571,7 @@ import gfx_isa::*;
 			retry <= wave.retry;
 			hold_valid <= wave.valid;
 
-			unique case (wave.insn.insn_class)
+			unique case (wave.insn.op_class)
 				INSN_FPINT: ; // p0 no tiene ready
 				INSN_MEM:   is_mem   <= 1;
 				INSN_SFU:   is_fsu   <= 1;
@@ -599,19 +597,22 @@ import gfx_isa::*;
 endmodule
 
 module gfx_shader_decode_fpint
-import gfx::*;
-import gfx_isa::*;
+import gfx::*, gfx_isa::*;
 (
-	input  logic     clk,
+	input  logic    clk,
 
-	input  insn_word insn,
-	input  logic     writeback,
+	input  insn_any insn,
+	input  logic    writeback,
 
-	output fpint_op  op
+	output fpint_op op
 );
 
+	insn_fpint as_fpint;
+
+	assign as_fpint = insn;
+
 	always_ff @(posedge clk) begin
-		unique case (insn.by_class.fpint.op)
+		unique case (as_fpint.op)
 			INSN_FPINT_MOV: begin
 				op.setup_mul_float    <= 0;
 				op.setup_unit_b       <= 1;
@@ -709,7 +710,7 @@ import gfx_isa::*;
 				op.mnorm_zero_flags   <= 0;
 				op.mnorm_zero_b       <= 0;
 				op.minmax_abs         <= 0;
-				op.minmax_swap        <= insn.by_class.fpint.op == INSN_FPINT_FMIN;
+				op.minmax_swap        <= as_fpint.op == INSN_FPINT_FMIN;
 				op.minmax_zero_min    <= 1;
 				op.minmax_copy_flags  <= 1;
 				op.shiftr_int_signed  <= 0;
diff --git a/rtl/gfx/gfx_shader_group.sv b/rtl/gfx/gfx_shader_group.sv
index 4a602a8..c4a9894 100644
--- a/rtl/gfx/gfx_shader_group.sv
+++ b/rtl/gfx/gfx_shader_group.sv
@@ -14,4 +14,6 @@ import gfx::*;
 	       gfx_wb.tx         wb
 );
 
+	word foo;
+
 endmodule
diff --git a/rtl/gfx/gfx_shader_mem.sv b/rtl/gfx/gfx_shader_mem.sv
index d9e4ff4..72ab0a4 100644
--- a/rtl/gfx/gfx_shader_mem.sv
+++ b/rtl/gfx/gfx_shader_mem.sv
@@ -14,4 +14,6 @@ import gfx::*;
 	       gfx_wb.tx         wb
 );
 
+	word foo;
+
 endmodule
diff --git a/rtl/gfx/gfx_shader_regs.sv b/rtl/gfx/gfx_shader_regs.sv
index ef3a129..2b3451a 100644
--- a/rtl/gfx/gfx_shader_regs.sv
+++ b/rtl/gfx/gfx_shader_regs.sv
@@ -33,7 +33,7 @@ import gfx::*;
 	assign pc_read_groups[1] = io.pc_front_group;
 
 	assign io.mask_back = mask_read[0];
-	assign pc_read_groups[0] = io.mask_back_group;
+	assign mask_read_groups[0] = io.mask_back_group;
 
 	assign imm_out = hold_imm[$size(hold_imm) - 1];
 	assign a_scalar_out = hold_a_scalar[$bits(hold_a_scalar) - 1];
@@ -83,20 +83,21 @@ import gfx::*;
 		.write_data(io.sgpr_write.data)
 	);
 
+	genvar gi;
 	generate
-		for (genvar i = 0; i < SHADER_LANES; ++i) begin: vgprs
+		for (gi = 0; gi < SHADER_LANES; ++gi) begin: vgprs
 			gfx_shader_regfile #($bits(group_id) + $bits(vgpr_num)) vgprs
 			(
 				.clk,
 
 				.read_a_num({hold_read_group_2, hold_read_a_vgpr_2}),
 				.read_b_num({hold_read_group_2, hold_read_b_vgpr_2}),
-				.read_a_data(read_a_data_vgpr[i]),
-				.read_b_data(read_b_data_vgpr[i]),
+				.read_a_data(read_a_data_vgpr[gi]),
+				.read_b_data(read_b_data_vgpr[gi]),
 
-				.write(io.vgpr_write.mask[i]),
+				.write(io.vgpr_write.mask[gi]),
 				.write_num({io.vgpr_write.group, io.vgpr_write.vgpr}),
-				.write_data(io.vgpr_write.data[i])
+				.write_data(io.vgpr_write.data[gi])
 			);
 		end
 	endgenerate
diff --git a/rtl/gfx/gfx_shader_setup.sv b/rtl/gfx/gfx_shader_setup.sv
index f46fb66..f437acb 100644
--- a/rtl/gfx/gfx_shader_setup.sv
+++ b/rtl/gfx/gfx_shader_setup.sv
@@ -1,5 +1,6 @@
-interface gfx_shader_setup
-import gfx::*;;
+interface gfx_shader_setup;
+
+	import gfx::*;
 
 	struct
 	{
diff --git a/rtl/gfx/gfx_shader_sfu.sv b/rtl/gfx/gfx_shader_sfu.sv
index f15ff04..0886449 100644
--- a/rtl/gfx/gfx_shader_sfu.sv
+++ b/rtl/gfx/gfx_shader_sfu.sv
@@ -14,4 +14,6 @@ import gfx::*;
 	       gfx_wb.tx         wb
 );
 
+	word foo;
+
 endmodule