diff options
| author | Alejandro Soto <alejandro@34project.org> | 2023-11-21 17:14:58 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-11-21 18:03:15 -0600 |
| commit | d2df92448a7aaaff9ae72f99bf4bcd00a6e55d8c (patch) | |
| tree | 7426719821476739dce9092dbc7cb2425c9efa5b /rtl/gfx/gfx_sp.sv | |
| parent | d076c33ffb6e3c0d96ee6b5dce0fcf48be8d3582 (diff) | |
rtl/gfx: implement SP issue
Diffstat (limited to 'rtl/gfx/gfx_sp.sv')
| -rw-r--r-- | rtl/gfx/gfx_sp.sv | 37 |
1 files changed, 20 insertions, 17 deletions
diff --git a/rtl/gfx/gfx_sp.sv b/rtl/gfx/gfx_sp.sv index 4adac7e..ce0f9ff 100644 --- a/rtl/gfx/gfx_sp.sv +++ b/rtl/gfx/gfx_sp.sv @@ -20,6 +20,7 @@ module gfx_sp input logic program_start, input cmd_word program_header_base, program_header_size, + output logic running, input logic send_ready, output logic send_valid, @@ -27,7 +28,7 @@ module gfx_sp output lane_mask send_mask ); - logic batch_start, clear_lanes, insn_valid, running; + logic batch_start, clear_lanes, insn_valid; cmd_word batch_length; insn_word insn; vram_insn_addr batch_base; @@ -47,6 +48,14 @@ module gfx_sp .* ); + logic deco_ready, combiner_issue_valid, shuffler_issue_valid, stream_issue_valid; + vreg_num rd_a_reg, rd_b_reg; + + gfx_sp_issue issue + ( + .* + ); + logic recv_valid; lane_word recv_data; lane_mask recv_mask; @@ -60,43 +69,40 @@ module gfx_sp .* ); - logic shuffler_wb_valid; + logic shuffler_issue_ready, shuffler_wb_valid; wb_op shuffler_wb; gfx_sp_shuffler shuffler ( .wb(shuffler_wb), - .deco(), - .in_ready(), - .in_valid(0), + .in_ready(shuffler_issue_ready), + .in_valid(shuffler_issue_valid), .wb_ready(shuffler_wb_ready), .wb_valid(shuffler_wb_valid), .* ); - logic combiner_wb_valid; + logic combiner_issue_ready, combiner_wb_valid; wb_op combiner_wb; gfx_sp_combiner combiner ( .wb(combiner_wb), - .deco(), - .in_ready(), - .in_valid(0), + .in_ready(combiner_issue_ready), + .in_valid(combiner_issue_valid), .wb_ready(combiner_wb_ready), .wb_valid(combiner_wb_valid), .* ); - logic recv_ready, stream_wb_valid; + logic recv_ready, stream_issue_ready, stream_wb_valid; wb_op stream_wb; gfx_sp_stream stream ( .wb(stream_wb), - .deco(), - .in_ready(), - .in_valid(0), + .in_ready(stream_issue_ready), + .in_valid(stream_issue_valid), .wb_ready(stream_wb_ready), .wb_valid(stream_wb_valid), .* @@ -115,14 +121,11 @@ module gfx_sp gfx_sp_regs regs ( - .rd_a_reg(), - .rd_b_reg(), .rd_a_data(a), .rd_b_data(b), .* ); - logic batch_end, deco_ready; - assign deco_ready = 1; + logic batch_end; endmodule |
