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authorAlejandro Soto <alejandro@34project.org>2024-02-28 16:44:15 -0600
committerAlejandro Soto <alejandro@34project.org>2024-03-03 20:42:36 -0600
commitcce507d21c86f20a83eec1b09fe3231399ffb10c (patch)
treecef497f3eb1767aeb9d8817adbbed467eac3b72d /rtl/dma_axi32/prgen_rawstat.v
parent872349eb3a3a508abee028e75da546692eb8e0e7 (diff)
rtl/dma_axi32: fix verilator warnings
Diffstat (limited to '')
-rw-r--r--rtl/dma_axi32/prgen_rawstat.v8
1 files changed, 6 insertions, 2 deletions
diff --git a/rtl/dma_axi32/prgen_rawstat.v b/rtl/dma_axi32/prgen_rawstat.v
index c1cd490..9e4fe47 100644
--- a/rtl/dma_axi32/prgen_rawstat.v
+++ b/rtl/dma_axi32/prgen_rawstat.v
@@ -1,3 +1,5 @@
+// verilator lint_off WIDTHEXPAND
+// verilator lint_off WIDTHTRUNC
/////////////////////////////////////////////////////////////////////
//// ////
//// Author: Eyal Hochberg ////
@@ -63,11 +65,13 @@ module prgen_rawstat (clk,reset,clear,write,pwdata,int_bus,rawstat);
always @(posedge clk or posedge reset)
if (reset)
- rawstat <= #1 {SIZE{1'b0}};
+ rawstat <= {SIZE{1'b0}};
else
- rawstat <= #1 (rawstat | int_bus | write_bus) & (~clear_bus);
+ rawstat <= (rawstat | int_bus | write_bus) & (~clear_bus);
endmodule
+// verilator lint_on WIDTHEXPAND
+// verilator lint_on WIDTHTRUNC