diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-08 13:02:33 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-08 13:02:33 -0600 |
| commit | a0a12ef0c1bd6882d902a9d5938e7220e543b378 (patch) | |
| tree | 9184e0161f3c803abe2d908b3864a443b458193c /rtl/core | |
| parent | 7e7c205367558b622fa56edaaa9c76491d57a4fa (diff) | |
Rename EXECUTE cycle as ISSUE
Diffstat (limited to 'rtl/core')
| -rw-r--r-- | rtl/core/cycles.sv | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv index 03c944f..ccf2d28 100644 --- a/rtl/core/cycles.sv +++ b/rtl/core/cycles.sv @@ -37,7 +37,7 @@ module core_cycles enum { - EXECUTE, + ISSUE, RD_INDIRECT_SHIFT, WITH_SHIFT } cycle, next_cycle; @@ -51,7 +51,7 @@ module core_cycles reg_num r_shift, final_rd; ptr pc; - assign stall = (next_cycle != EXECUTE) | bubble; + assign stall = (next_cycle != ISSUE) | bubble; assign pc_visible = pc + 2; assign reg_mode = `MODE_SVC; //TODO @@ -65,10 +65,10 @@ module core_cycles if(final_writeback & (shifter.shl | shifter.shr | shifter.ror)) trivial_shift = shifter_shift == 0; - next_cycle = EXECUTE; + next_cycle = ISSUE; unique case(cycle) - EXECUTE: + ISSUE: if(data_snd_shift_by_reg) next_cycle = RD_INDIRECT_SHIFT; else if(~trivial_shift) @@ -82,10 +82,10 @@ module core_cycles endcase if(bubble) - next_cycle = EXECUTE; + next_cycle = ISSUE; unique case(cycle) - EXECUTE: + ISSUE: if(data_snd_is_imm) alu_b = {{24{1'b0}}, data_imm}; else @@ -103,7 +103,7 @@ module core_cycles wr_value <= q_alu; unique case(next_cycle) - EXECUTE: begin + ISSUE: begin branch <= 0; branch_target <= {30{1'bx}}; final_writeback <= 0; @@ -160,7 +160,7 @@ module core_cycles end initial begin - cycle = EXECUTE; + cycle = ISSUE; bubble = 0; pc = 0; |