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authorAlejandro Soto <alejandro@34project.org>2022-10-16 01:33:43 -0600
committerAlejandro Soto <alejandro@34project.org>2022-10-16 01:33:43 -0600
commitf0b38daac3a2f987deb79fcca763f3b84b0f2b73 (patch)
tree7dda62ccee3ced8deddaf7926f0663b83de1ab90 /rtl/core
parent0782a4f841a15f60c99d817cf82ce4fd3c2e9e3d (diff)
Move isa.sv to core/decode
Diffstat (limited to 'rtl/core')
-rw-r--r--rtl/core/decode/branch.sv2
-rw-r--r--rtl/core/decode/conds.sv2
-rw-r--r--rtl/core/decode/data.sv2
-rw-r--r--rtl/core/decode/decode.sv2
-rw-r--r--rtl/core/decode/isa.sv (renamed from rtl/core/isa.sv)4
-rw-r--r--rtl/core/decode/ldst/misc.sv2
-rw-r--r--rtl/core/decode/ldst/multiple.sv2
-rw-r--r--rtl/core/decode/ldst/single.sv2
-rw-r--r--rtl/core/decode/snd.sv2
9 files changed, 10 insertions, 10 deletions
diff --git a/rtl/core/decode/branch.sv b/rtl/core/decode/branch.sv
index 9916374..1dbc1ad 100644
--- a/rtl/core/decode/branch.sv
+++ b/rtl/core/decode/branch.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
`include "core/uarch.sv"
module core_decode_branch
diff --git a/rtl/core/decode/conds.sv b/rtl/core/decode/conds.sv
index 564ed27..60922a0 100644
--- a/rtl/core/decode/conds.sv
+++ b/rtl/core/decode/conds.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
`include "core/uarch.sv"
module core_decode_conds
diff --git a/rtl/core/decode/data.sv b/rtl/core/decode/data.sv
index e2a44df..cb21f5e 100644
--- a/rtl/core/decode/data.sv
+++ b/rtl/core/decode/data.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
`include "core/uarch.sv"
module core_decode_data
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index 73d3b59..5e72afe 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
`include "core/uarch.sv"
module core_decode
diff --git a/rtl/core/isa.sv b/rtl/core/decode/isa.sv
index c98cfd9..baaf371 100644
--- a/rtl/core/isa.sv
+++ b/rtl/core/decode/isa.sv
@@ -1,5 +1,5 @@
-`ifndef CORE_ISA_SV
-`define CORE_ISA_SV
+`ifndef CORE_DECODE_ISA_SV
+`define CORE_DECODE_ISA_SV
`define FIELD_COND [31:28]
`define FIELD_OP [27:0]
diff --git a/rtl/core/decode/ldst/misc.sv b/rtl/core/decode/ldst/misc.sv
index f2fe258..d8ac898 100644
--- a/rtl/core/decode/ldst/misc.sv
+++ b/rtl/core/decode/ldst/misc.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
`include "core/uarch.sv"
module core_decode_ldst_misc
diff --git a/rtl/core/decode/ldst/multiple.sv b/rtl/core/decode/ldst/multiple.sv
index d286a67..201f333 100644
--- a/rtl/core/decode/ldst/multiple.sv
+++ b/rtl/core/decode/ldst/multiple.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
`include "core/uarch.sv"
module core_decode_ldst_multiple
diff --git a/rtl/core/decode/ldst/single.sv b/rtl/core/decode/ldst/single.sv
index 0665178..402c17b 100644
--- a/rtl/core/decode/ldst/single.sv
+++ b/rtl/core/decode/ldst/single.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
`include "core/uarch.sv"
module core_decode_ldst_single
diff --git a/rtl/core/decode/snd.sv b/rtl/core/decode/snd.sv
index 4dbb028..4e8de96 100644
--- a/rtl/core/decode/snd.sv
+++ b/rtl/core/decode/snd.sv
@@ -1,4 +1,4 @@
-`include "core/isa.sv"
+`include "core/decode/isa.sv"
`include "core/uarch.sv"
module core_decode_snd