Implement flag updates

4 files changed, 28 insertions, 8 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index b37057d..4a970d9 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -28,7 +28,7 @@ module arm810
 		.*
 	);
 
-	logic decode_execute, decode_undefined, decode_writeback, decode_branch;
+	logic decode_execute, decode_undefined, decode_writeback, decode_branch, decode_update_flags;
 	ptr decode_branch_offset;
 	reg_num decode_rd;
 	alu_op decode_data_op;
@@ -39,15 +39,16 @@ module arm810
 		.execute(decode_execute),
 		.undefined(decode_undefined),
 		.writeback(decode_writeback),
-		.rd(decode_rd),
 		.branch(decode_branch),
+		.update_flags(decode_update_flags),
+		.rd(decode_rd),
 		.branch_offset(decode_branch_offset),
 		.data_op(decode_data_op),
 		.*
 	);
 
 	reg_num rd;
-	logic explicit_branch, writeback;
+	logic explicit_branch, writeback, update_flags;
 	ptr branch_target;
 	psr_mode reg_mode;
 	alu_op data_op;
@@ -81,6 +82,7 @@ module arm810
 	);
 
 	psr_flags alu_flags;
+	logic alu_v_valid;
 
 	core_alu #(.W(32)) alu
 	(
@@ -90,7 +92,7 @@ module arm810
 		.c_in(flags.c),
 		.q(wr_value),
 		.nzcv(alu_flags),
-		.v_valid() //TODO
+		.v_valid(alu_v_valid)
 	);
 
 endmodule
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
index 0f6ce15..726a40a 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/cycles.sv
@@ -4,8 +4,9 @@ module core_cycles
 (
 	input  logic     clk,
 	                 decode_execute,
-	                 decode_writeback,
 	                 decode_branch,
+	                 decode_writeback,
+	                 decode_update_flags,
 	input  reg_num   decode_rd,
 	input  ptr       decode_branch_offset,
 	input  alu_op    decode_data_op,
@@ -14,6 +15,7 @@ module core_cycles
 	output logic     stall,
 	                 branch,
 	                 writeback,
+	                 update_flags,
 	output reg_num   rd,
 	output ptr       branch_target,
 	                 pc,
@@ -38,6 +40,7 @@ module core_cycles
 		if(next_cycle == EXECUTE) begin
 			branch <= 0;
 			writeback <= 0;
+			update_flags <= 0;
 			branch_target <= 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
 
 			if(decode_execute) begin
@@ -49,6 +52,7 @@ module core_cycles
 			pc <= fetch_insn_pc;
 			rd <= decode_rd;
 			data_op <= decode_data_op;
+			update_flags <= decode_update_flags;
 		end
 	end
 
diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index 6b9b3b5..fad7edc 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -9,6 +9,7 @@ module core_decode
 	output logic     execute,
 	                 undefined,
 	                 writeback,
+	                 update_flags,
 	                 branch,
 	output ptr       branch_offset,
 	output reg_num   rd,
@@ -36,9 +37,9 @@ module core_decode
 
 	//TODO
 	reg_num rn;
-	logic update_flags, restore_spsr, zero_fst, negate_fst, negate_snd, carry_in;
+	logic restore_spsr;
 
-	logic data_writeback;
+	logic data_writeback, data_update_flags;
 	reg_num data_rd;
 	alu_op data_group_op;
 
@@ -47,6 +48,7 @@ module core_decode
 		.op(data_group_op),
 		.rd(data_rd),
 		.writeback(data_writeback),
+		.update_flags(data_update_flags),
 		.*
 	);
 
@@ -55,6 +57,7 @@ module core_decode
 
 		branch = 0;
 		writeback = 0;
+		update_flags = 0;
 		rd = 4'bxxxx;
 		data_op = 4'bxxxx;
 
@@ -72,6 +75,7 @@ module core_decode
 				rd = data_rd;
 				writeback = data_writeback;
 				data_op = data_group_op;
+				update_flags = data_update_flags;
 			end
 
 			`INSN_MUL: ;
diff --git a/rtl/core/psr.sv b/rtl/core/psr.sv
index 0ade723..2c0d48f 100644
--- a/rtl/core/psr.sv
+++ b/rtl/core/psr.sv
@@ -3,13 +3,23 @@
 module core_psr
 (
 	input  logic     clk,
+	                 update_flags,
+	                 alu_v_valid,
 	input  psr_flags alu_flags,
 
 	output psr_flags flags,
 	                 next_flags
 );
 
-	assign next_flags = alu_flags; //TODO
+	always_comb begin
+		next_flags = flags;
+
+		if(update_flags) begin
+			next_flags = alu_flags;
+			if(~alu_v_valid)
+				next_flags.v = flags.v;
+		end
+	end
 
 	always_ff @(posedge clk)
 		flags <= next_flags;