tb: implement quad-core SMP

2 files changed, 4 insertions, 8 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 6f798f4..f498a15 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -7,8 +7,8 @@ module arm810
 	                  rst_n,
 
 	input  logic      irq,
-	                  halt,
-	                  step,
+	                  halt /*verilator public*/ /*verilator forceable*/,
+	                  step /*verilator public*/ /*verilator forceable*/,
 
 	output ptr        bus_addr,
 	output logic      bus_start,
@@ -18,8 +18,8 @@ module arm810
 	output word       bus_data_wr,
 	output logic[3:0] bus_data_be,
 
-	output logic      halted,
-	                  breakpoint
+	output logic      halted /*verilator public*/,
+	                  breakpoint /*verilator public*/
 );
 
 	ptr branch_target, fetch_insn_pc, fetch_head, insn_addr;
diff --git a/rtl/core/core.sv b/rtl/core/core.sv
index 8d487fa..3703fe4 100644
--- a/rtl/core/core.sv
+++ b/rtl/core/core.sv
@@ -45,10 +45,6 @@ module core
 		.bus_ready(ready),
 		.bus_write(write),
 		.bus_start(start),
-`ifndef VERILATOR
-		.step(0),
-		.breakpoint(),
-`endif
 		.*
 	);