rtl/core, tb: replace bus_master with a new top-level module

8 files changed, 42 insertions, 24 deletions

diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul_fu.sv
index 8352435..8352435 100644
--- a/rtl/core/control/mul.sv
+++ b/rtl/core/control/mul_fu.sv
diff --git a/rtl/core/control/psr.sv b/rtl/core/control/status.sv
index 6616bc9..6616bc9 100644
--- a/rtl/core/control/psr.sv
+++ b/rtl/core/control/status.sv
diff --git a/rtl/bus_master.sv b/rtl/core/core.sv
index 0c6af55..8d487fa 100644
--- a/rtl/bus_master.sv
+++ b/rtl/core/core.sv
@@ -1,38 +1,56 @@
-module bus_master
+`include "core/uarch.sv"
+
+module core
 (
-	input  logic       clk,
-	                   rst_n,
+	input  logic      clk,
+	                  rst_n,
+
+	input  wire       step,
+	input  wire       cpu_halt,
+	output wire       cpu_halted,
+	output wire       breakpoint,
 
-	input  logic[29:0] addr,
-	input  logic       start,
-	                   write,
-	output logic       ready,
-	output logic[31:0] data_rd,
-	input  logic[31:0] data_wr,
-	input  logic[3:0]  data_be,
-	output logic       cpu_clk,
-	                   cpu_rst_n,
-	                   irq,
+	output word       avl_address,
+	output logic      avl_read,
+	                  avl_write,
+	input  word       avl_readdata,
+	output word       avl_writedata,
+	input  logic      avl_waitrequest,
+	output logic[3:0] avl_byteenable,
 
-	output logic[31:0] avl_address,
-	output logic       avl_read,
-	                   avl_write,
-	input  logic[31:0] avl_readdata,
-	output logic[31:0] avl_writedata,
-	input  logic       avl_waitrequest,
-	output logic[3:0]  avl_byteenable,
-	input  logic       avl_irq
+	input  logic      avl_irq
 );
 
+	logic ready, write, start;
+
+	logic[3:0] data_be;
+	logic[29:0] addr;
+	logic[31:0] data_rd, data_wr;
+
 	enum int unsigned
 	{
 		IDLE,
 		WAIT
 	} state;
 
-	assign irq = avl_irq;
-	assign cpu_clk = clk;
-	assign cpu_rst_n = rst_n;
+	arm810 cpu
+	(
+		.irq(avl_irq),
+		.halt(cpu_halt),
+		.halted(cpu_halted),
+		.bus_addr(addr),
+		.bus_data_rd(data_rd),
+		.bus_data_wr(data_wr),
+		.bus_data_be(data_be),
+		.bus_ready(ready),
+		.bus_write(write),
+		.bus_start(start),
+`ifndef VERILATOR
+		.step(0),
+		.breakpoint(),
+`endif
+		.*
+	);
 
 	assign data_rd = avl_readdata;
 
diff --git a/rtl/core/decode/branch.sv b/rtl/core/decode/branch_dec.sv
index 1dbc1ad..1dbc1ad 100644
--- a/rtl/core/decode/branch.sv
+++ b/rtl/core/decode/branch_dec.sv
diff --git a/rtl/core/decode/coproc.sv b/rtl/core/decode/coproc_dec.sv
index 153cadf..153cadf 100644
--- a/rtl/core/decode/coproc.sv
+++ b/rtl/core/decode/coproc_dec.sv
diff --git a/rtl/core/decode/data.sv b/rtl/core/decode/data_dec.sv
index f744972..f744972 100644
--- a/rtl/core/decode/data.sv
+++ b/rtl/core/decode/data_dec.sv
diff --git a/rtl/core/decode/mul.sv b/rtl/core/decode/mul_dec.sv
index 114b65b..114b65b 100644
--- a/rtl/core/decode/mul.sv
+++ b/rtl/core/decode/mul_dec.sv
diff --git a/rtl/core/regs/map.sv b/rtl/core/regs/reg_map.sv
index 11085d4..11085d4 100644
--- a/rtl/core/regs/map.sv
+++ b/rtl/core/regs/reg_map.sv