Implement initial cycle control logic

2 files changed, 113 insertions, 14 deletions

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 4c72fa2..82479d1 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -1,38 +1,77 @@
+`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module arm810
 (
-	input  logic       clk,
-
-	output logic[29:0] bus_addr,
-	output logic       bus_start,
-	                   bus_write,
-	input  logic       bus_ready,
-	input  logic[31:0] bus_data_rd,
-	output logic[31:0] bus_data_wr
+	input  logic clk,
+
+	output ptr   bus_addr,
+	output logic bus_start,
+	             bus_write,
+	input  logic bus_ready,
+	input  word  bus_data_rd,
+	output word  bus_data_wr
 );
 
 	logic stall, prefetch_flush;
-	logic[31:0] insn;
-	logic[29:0] insn_pc;
+	word insn;
+	ptr fetch_insn_pc, pc, pc_visible;
 
 	psr_flags flags;
-	assign flags = 4'b1010;
+	assign flags = 4'b1010; //TODO
 
 	core_fetch #(.PREFETCH_ORDER(2)) fetch
 	(
-		.flush(prefetch_flush),
+		.flush(explicit_branch | wr_pc),
+		.target(wr_pc ? wr_value[29:0] : branch_target),
 		.addr(bus_addr),
 		.fetched(bus_ready),
 		.fetch_data(bus_data_rd),
 		.fetch(bus_start),
+		.insn_pc(fetch_insn_pc),
 		.*
 	);
 
-	//TODO
-	logic execute, undefined;
+	logic decode_execute, decode_undefined, decode_writeback, decode_branch;
+	ptr decode_branch_offset;
+	reg_num decode_rd;
+
 	core_decode decode
 	(
+		.execute(decode_execute),
+		.undefined(decode_undefined),
+		.writeback(decode_writeback),
+		.rd(decode_rd),
+		.branch(decode_branch),
+		.branch_offset(decode_branch_offset),
+		.*
+	);
+
+	reg_num rd;
+	logic explicit_branch, writeback;
+	ptr branch_target;
+	psr_mode reg_mode;
+
+	core_cycles cycles
+	(
+		.branch(explicit_branch),
+		.*
+	);
+
+	logic wr_pc;
+	word wr_value;
+
+	core_regs regs
+	(
+		.rd_r_a(0), //TODO
+		.rd_r_b(0), //TODO
+		.rd_value_a(), //TODO
+		.rd_value_b(), //TODO
+		.rd_mode(reg_mode),
+		.wr_mode(reg_mode),
+		.wr_r(rd),
+		.wr_enable(writeback),
+		.branch(wr_pc),
 		.*
 	);
 
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
new file mode 100644
index 0000000..64d77e6
--- /dev/null
+++ b/rtl/core/cycles.sv
@@ -0,0 +1,60 @@
+`include "core/uarch.sv"
+
+module core_cycles
+(
+	input  logic    clk,
+	                decode_execute,
+	                decode_writeback,
+	                decode_branch,
+	input  ptr      decode_branch_offset,
+	input  reg_num  decode_rd,
+	input  ptr      fetch_insn_pc,
+
+	output logic    stall,
+	                branch,
+	                writeback,
+	output ptr      branch_target,
+	                pc,
+	                pc_visible,
+	output psr_mode reg_mode
+);
+
+	enum
+	{
+		EXECUTE
+	} cycle, next_cycle;
+
+	assign stall = next_cycle != EXECUTE;
+	assign pc_visible = pc + 2;
+	assign next_cycle = EXECUTE; //TODO
+	assign reg_mode = `MODE_SVC; //TODO
+
+	always_ff @(posedge clk) begin
+		cycle <= next_cycle;
+		stall <= next_cycle != EXECUTE;
+
+		if(next_cycle == EXECUTE) begin
+			branch <= 0;
+			writeback <= 0;
+			branch_target <= 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
+
+			if(decode_execute) begin
+				branch <= decode_branch;
+				writeback <= decode_writeback;
+				branch_target <= pc_visible + decode_branch_offset;
+			end
+
+			pc <= fetch_insn_pc;
+		end
+	end
+
+	initial begin
+		cycle = EXECUTE;
+
+		branch = 1;
+		writeback = 0;
+		branch_target = 30'd0;
+		pc = 0;
+	end
+
+endmodule