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| author | Alejandro Soto <alejandro@34project.org> | 2022-09-25 19:55:29 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-09-25 19:55:29 -0600 |
| commit | fa370016708149976c748c14eadad1f89cf5a8ea (patch) | |
| tree | 785ca92bebaef645e15f26a97d4892ef2ba2dad9 /rtl/core/uarch.sv | |
| parent | 3aa075cf009d9aa8c602389853cc3ea78cda8701 (diff) | |
Refactor CPSR and uarch.sv
Diffstat (limited to 'rtl/core/uarch.sv')
| -rw-r--r-- | rtl/core/uarch.sv | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/rtl/core/uarch.sv b/rtl/core/uarch.sv index be67bd5..07b479d 100644 --- a/rtl/core/uarch.sv +++ b/rtl/core/uarch.sv @@ -4,9 +4,13 @@ // Decodifica como andeq r0, r0, r0 `define NOP 32'd0 +typedef logic[3:0] reg_num; typedef logic[31:0] word; typedef logic[29:0] ptr; +`define R14 4'b1110 +`define R15 4'b1111 + /* Se necesitan 30 GPRs. De A2.3: * * The ARM processor has a total of 37 registers: @@ -37,4 +41,19 @@ typedef logic[3:0] alu_op; `define ALU_BIC 4'b1110 `define ALU_MVN 4'b1111 +typedef struct packed +{ + logic n, z, c, v; +} psr_flags; + +typedef logic[4:0] psr_mode; + +`define MODE_USR 5'b10000 +`define MODE_FIQ 5'b10001 +`define MODE_IRQ 5'b10010 +`define MODE_SVC 5'b10011 +`define MODE_ABT 5'b10111 +`define MODE_UND 5'b11011 +`define MODE_SYS 5'b11111 + `endif |