Rework regfile in order to remove negedge trigger

2 files changed, 46 insertions, 39 deletions

diff --git a/rtl/core/regs/file.sv b/rtl/core/regs/file.sv
index e0f9b4c..38c3301 100644
--- a/rtl/core/regs/file.sv
+++ b/rtl/core/regs/file.sv
@@ -3,27 +3,47 @@
 module core_reg_file
 (
 	input  logic     clk,
-	input  reg_index rd_index,
-	                 wr_index,
+	input  psr_mode  rd_mode,
+	input  reg_num   rd_r,
+	input  reg_index wr_index,
 	input  logic     wr_enable,
+	                 wr_enable_file,
 	input  word      wr_value,
+	                 wr_current,
+	                 pc_word,
 
 	output word      rd_value
 );
 
 	// Ver comentario en uarch.sv
-	word file[30] /*verilator public*/;
+	word file[`NUM_GPREGS] /*verilator public*/;
+	word rd_actual;
+	logic rd_pc, hold_rd_pc, forward;
+	reg_index rd_index;
+
+	core_reg_map map_rd
+	(
+		.r(rd_r),
+		.mode(rd_mode),
+		.is_pc(rd_pc),
+		.index(rd_index)
+	);
+
+	assign rd_value = hold_rd_pc ? pc_word : forward ? wr_current : rd_actual;
 
-	//FIXME: Esto claramente no sirve
-`ifdef VERILATOR
-	always_ff @(negedge clk) begin
-`else
 	always_ff @(posedge clk) begin
-`endif
-		if(wr_enable)
+		forward <= wr_enable && rd_index == wr_index;
+		hold_rd_pc <= rd_pc;
+
+		if(wr_enable_file)
 			file[wr_index] <= wr_value;
 
-		rd_value <= file[rd_index];
+		rd_actual <= file[rd_index];
+	end
+
+	initial begin
+		forward = 0;
+		hold_rd_pc = 0;
 	end
 
 endmodule
diff --git a/rtl/core/regs/regs.sv b/rtl/core/regs/regs.sv
index 9b9ba57..b25a122 100644
--- a/rtl/core/regs/regs.sv
+++ b/rtl/core/regs/regs.sv
@@ -23,48 +23,28 @@ module core_regs
 	 * sincronizadas del archivo de registros.
 	 */
 
-	logic rd_pc_a, rd_pc_b, wr_pc, file_wr_enable;
-	reg_index rd_index_a, rd_index_b, wr_index;
-	word pc_word, file_rd_value_a, file_rd_value_b;
+	word pc_word, wr_current;
+	logic wr_pc, wr_enable_file;
+	reg_index wr_index;
 
+	assign branch = wr_enable && wr_pc;
 	assign pc_word = {pc_visible, 2'b00};
-	assign rd_value_a = rd_pc_a ? pc_word : (wr_enable && rd_index_a == wr_index) ? wr_value : file_rd_value_a;
-	assign rd_value_b = rd_pc_b ? pc_word : (wr_enable && rd_index_b == wr_index) ? wr_value : file_rd_value_b;
-	assign file_wr_enable = wr_enable & ~wr_pc;
-	assign branch = wr_enable & wr_pc;
+	assign wr_enable_file = wr_enable && !wr_pc;
 
 	core_reg_file a
 	(
-		.rd_index(rd_index_a),
-		.rd_value(file_rd_value_a),
-		.wr_enable(file_wr_enable),
+		.rd_r(rd_r_a),
+		.rd_value(rd_value_a),
 		.*
 	);
 
 	core_reg_file b
 	(
-		.rd_index(rd_index_b),
-		.rd_value(file_rd_value_b),
-		.wr_enable(file_wr_enable),
+		.rd_r(rd_r_b),
+		.rd_value(rd_value_b),
 		.*
 	);
 
-	core_reg_map map_rd_a
-	(
-		.r(rd_r_a),
-		.mode(rd_mode),
-		.is_pc(rd_pc_a),
-		.index(rd_index_a)
-	);
-
-	core_reg_map map_rd_b
-	(
-		.r(rd_r_b),
-		.mode(rd_mode),
-		.is_pc(rd_pc_b),
-		.index(rd_index_b)
-	);
-
 	core_reg_map map_wr
 	(
 		.r(wr_r),
@@ -73,4 +53,11 @@ module core_regs
 		.index(wr_index)
 	);
 
+	always_ff @(posedge clk)
+		if(wr_enable)
+			wr_current <= wr_value;
+
+	initial
+		wr_current = 0;
+
 endmodule