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authorAlejandro Soto <alejandro@34project.org>2022-11-08 13:00:40 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-08 13:29:23 -0600
commitf6929f9a4703e3eee9d7bd9752de055729cdd498 (patch)
tree770acb4f96fd16e0f12bec2c5ed5cfdfa5a4c315 /rtl/core/porch
parent89a8edd4bb96787c69118dd5f549345015b2d480 (diff)
Register decode output in a new porch stage
Diffstat (limited to '')
-rw-r--r--rtl/core/porch/conds.sv (renamed from rtl/core/decode/conds.sv)6
-rw-r--r--rtl/core/porch/porch.sv53
2 files changed, 56 insertions, 3 deletions
diff --git a/rtl/core/decode/conds.sv b/rtl/core/porch/conds.sv
index 60922a0..b8db1e7 100644
--- a/rtl/core/decode/conds.sv
+++ b/rtl/core/porch/conds.sv
@@ -1,9 +1,9 @@
`include "core/decode/isa.sv"
`include "core/uarch.sv"
-module core_decode_conds
+module core_porch_conds
(
- input logic[3:0] cond,
+ input word insn,
input psr_flags flags,
output logic execute,
@@ -15,7 +15,7 @@ module core_decode_conds
undefined = 0;
conditional = 1;
- unique case(cond)
+ unique case(insn `FIELD_COND)
`COND_EQ: execute = flags.z;
`COND_NE: execute = ~flags.z;
`COND_HS: execute = flags.c;
diff --git a/rtl/core/porch/porch.sv b/rtl/core/porch/porch.sv
new file mode 100644
index 0000000..6f5caf7
--- /dev/null
+++ b/rtl/core/porch/porch.sv
@@ -0,0 +1,53 @@
+`include "core/uarch.sv"
+
+module core_porch
+(
+ input logic clk,
+ flush,
+ stall,
+ input psr_flags flags,
+
+ input word fetch_insn,
+ input ptr fetch_insn_pc,
+ input insn_decode fetch_dec,
+
+ output word insn,
+ output ptr insn_pc,
+ output insn_decode dec
+);
+
+ logic execute, conditional, undefined;
+ insn_decode nop, hold_dec;
+
+ core_porch_conds conds
+ (
+ .*
+ );
+
+ assign nop.ctrl.execute = 0;
+ assign nop.ctrl.undefined = 0;
+ assign nop.ctrl.conditional = 0;
+
+ always_comb begin
+ dec = hold_dec;
+ dec.ctrl.execute = !flush && dec.ctrl.execute && execute;
+ dec.ctrl.undefined = !flush && (dec.ctrl.undefined || undefined);
+ dec.ctrl.conditional = !flush && (dec.ctrl.conditional || conditional);
+ end
+
+ always @(posedge clk)
+ if(!stall) begin
+ insn <= fetch_insn;
+ hold_dec <= fetch_dec;
+
+ if(!flush)
+ insn_pc <= fetch_insn_pc;
+ end
+
+ initial begin
+ insn = `NOP;
+ insn_pc = 0;
+ hold_dec = nop;
+ end
+
+endmodule