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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-07 12:57:48 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-07 13:31:15 -0600 |
| commit | aaf02562e4d49fc93df1f619e3fbd6c85c0e7951 (patch) | |
| tree | d7ae1d53f18950d370def5932553947c3af4f785 /rtl/core/mul.sv | |
| parent | f78de55eef2e805e459064005daa08c7697d2273 (diff) | |
Implement multiplication control
Diffstat (limited to 'rtl/core/mul.sv')
| -rw-r--r-- | rtl/core/mul.sv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/rtl/core/mul.sv b/rtl/core/mul.sv index 616905f..a801851 100644 --- a/rtl/core/mul.sv +++ b/rtl/core/mul.sv @@ -23,7 +23,7 @@ module core_mul logic wait_state; dword c, q; - assign ready = wait_state == {$bits(wait_state){1'b0}}; + assign ready = !start && wait_state == {$bits(wait_state){1'b0}}; assign {q_hi, q_lo} = q; assign n = long_mul ? q_hi[$bits(q_hi) - 1] : q_lo[$bits(q_lo) - 1]; assign z = q_lo == 0 && (!long_mul || q_hi == 0); @@ -31,7 +31,7 @@ module core_mul dsp_mul ip ( .clock0(clk), - .aclr0(0), //TODO + .aclr0(1), //TODO .ena0(start || !ready), .dataa_0(a), .datab_0(b), |