rtl: implement exclusive monitor datapath

1 files changed, 12 insertions, 1 deletions

diff --git a/rtl/core/mmu/arbiter.sv b/rtl/core/mmu/arbiter.sv
index 5a75ddf..b0da7c8 100644
--- a/rtl/core/mmu/arbiter.sv
+++ b/rtl/core/mmu/arbiter.sv
@@ -4,6 +4,7 @@ module core_mmu_arbiter
 	                  rst_n,
 
 	input  logic      bus_ready,
+	                  bus_ex_fail,
 	input  word       bus_data_rd,
 	                  data_data_wr,
 	input  ptr        insn_addr,
@@ -11,6 +12,7 @@ module core_mmu_arbiter
 	input  logic      insn_start,
 	                  data_start,
 	                  data_write,
+	                  data_ex_lock,
 	input  logic[3:0] data_data_be,
 
 	output word       bus_data_wr,
@@ -18,8 +20,10 @@ module core_mmu_arbiter
 	output ptr        bus_addr,
 	output logic      bus_start,
 	                  bus_write,
+	                  bus_ex_lock,
 	                  insn_ready,
 	                  data_ready,
+	                  data_ex_fail,
 	output word       insn_data_rd,
 	                  data_data_rd
 );
@@ -32,9 +36,10 @@ module core_mmu_arbiter
 
 	ptr hold_addr;
 	word hold_data_wr;
-	logic active, hold_start, hold_write, hold_issue, hold_free, transition;
+	logic active, hold_ex_lock, hold_start, hold_write, hold_issue, hold_free, transition;
 	logic[3:0] hold_data_be;
 
+	assign data_ex_fail = bus_ex_fail;
 	assign insn_data_rd = bus_data_rd;
 	assign data_data_rd = bus_data_rd;
 
@@ -66,6 +71,7 @@ module core_mmu_arbiter
 				bus_write = 0;
 				bus_start = insn_start;
 				bus_data_be = 4'b1111;
+				bus_ex_lock = 0;
 			end
 
 			DATA: begin
@@ -73,6 +79,7 @@ module core_mmu_arbiter
 				bus_write = data_write;
 				bus_start = data_start;
 				bus_data_be = data_data_be;
+				bus_ex_lock = data_ex_lock;
 			end
 		endcase
 
@@ -82,6 +89,7 @@ module core_mmu_arbiter
 			bus_start = 1;
 			bus_data_wr = hold_data_wr;
 			bus_data_be = hold_data_be;
+			bus_ex_lock = hold_ex_lock;
 		end
 	end
 
@@ -95,6 +103,7 @@ module core_mmu_arbiter
 			hold_write <= 0;
 			hold_data_wr <= 0;
 			hold_data_be <= 0;
+			hold_ex_lock <= 0;
 		end else begin
 			master <= next_master;
 			active <= bus_start || (active && !bus_ready);
@@ -107,6 +116,7 @@ module core_mmu_arbiter
 						hold_write <= data_write;
 						hold_data_wr <= data_data_wr;
 						hold_data_be <= data_data_be;
+						hold_ex_lock <= data_ex_lock;
 					end
 
 					DATA: begin
@@ -114,6 +124,7 @@ module core_mmu_arbiter
 						hold_start <= insn_start;
 						hold_write <= 0;
 						hold_data_be <= 4'b1111;
+						hold_ex_lock <= 0;
 					end
 				endcase
 		end