Rework bus architecture

2 files changed, 15 insertions, 14 deletions

diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv
index a57c679..e8c6a9b 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/fetch/fetch.sv
@@ -17,7 +17,7 @@ module core_fetch
 	             addr
 );
 
-	ptr next_pc, head;
+	ptr next_pc, head, hold_addr;
 	logic fetched_valid, do_flush, discard;
 
 	assign do_flush = branch | flush;
@@ -30,7 +30,7 @@ module core_fetch
 		.*
 	);
 
-	always_comb
+	always_comb begin
 		if(branch)
 			head = target;
 		else if(flush)
@@ -38,17 +38,21 @@ module core_fetch
 		else
 			head = {30{1'bx}};
 
-	always_ff @(posedge clk) begin
 		if(do_flush)
-			addr <= head;
+			addr = head;
 		else if(fetched_valid)
-			addr <= addr + 1;
+			addr = hold_addr + 1;
+		else
+			addr = hold_addr;
+	end
 
+	always_ff @(posedge clk) begin
 		discard <= discard ? ~fetched : do_flush & fetch;
+		hold_addr <= addr;
 	end
 
 	initial begin
-		addr = 0;
+		hold_addr = 0;
 		discard = 0;
 	end
 
diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv
index 486ec96..4025339 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/fetch/prefetch.sv
@@ -23,19 +23,16 @@ module core_prefetch
 
 	assign insn = flush ? `NOP : prefetch[0];
 	assign next_pc = ~stall & |valid ? insn_pc + 1 : insn_pc;
-
-	always_comb
-		if((valid == SIZE - 2) & fetched)
-			fetch = 0;
-		else
-			fetch = ~&valid;
+	assign fetch = !stall || ~&valid;
 
 	always_ff @(posedge clk) begin
 		insn_pc <= flush ? head : next_pc;
 
-		if(~flush & fetched & (valid == SIZE - 1))
+		if(flush)
+			prefetch[SIZE - 1] <= `NOP;
+		else if(fetched && valid == SIZE - 1 + {{(ORDER - 1){1'b0}}, !stall})
 			prefetch[SIZE - 1] <= fetch_data;
-		else
+		else if(!stall)
 			prefetch[SIZE - 1] <= `NOP;
 
 		if(flush)