Implement register writes from gdb

1 files changed, 2 insertions, 2 deletions

diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv
index c024e7d..ba9d677 100644
--- a/rtl/core/fetch/fetch.sv
+++ b/rtl/core/fetch/fetch.sv
@@ -7,7 +7,7 @@ module core_fetch
 	             rst_n,
 	             stall,
 	             fetched,
-	             explicit_branch,
+	             explicit_branch /*verilator public*/ /*verilator forceable*/,
 	             wr_pc,
 	             prefetch_flush,
 	input  ptr   branch_target,
@@ -24,7 +24,7 @@ module core_fetch
 	             fetch_head
 );
 
-	ptr hold_addr, target;
+	ptr target /*verilator public*/ /*verilator forceable*/, hold_addr;
 	logic branch, prefetch_ready, fetched_valid, discard, pending, next_pending;
 
 	assign fetch = prefetch_ready && !discard;