Implement reset

1 files changed, 25 insertions, 25 deletions

diff --git a/rtl/core/fetch/prefetch.sv b/rtl/core/fetch/prefetch.sv
index 4025339..2f0a866 100644
--- a/rtl/core/fetch/prefetch.sv
+++ b/rtl/core/fetch/prefetch.sv
@@ -4,6 +4,7 @@ module core_prefetch
 #(parameter ORDER=2)
 (
 	input  logic clk,
+	             rst_n,
 	             stall,
 	             flush,
 	             fetched,
@@ -25,43 +26,42 @@ module core_prefetch
 	assign next_pc = ~stall & |valid ? insn_pc + 1 : insn_pc;
 	assign fetch = !stall || ~&valid;
 
-	always_ff @(posedge clk) begin
-		insn_pc <= flush ? head : next_pc;
-
-		if(flush)
-			prefetch[SIZE - 1] <= `NOP;
-		else if(fetched && valid == SIZE - 1 + {{(ORDER - 1){1'b0}}, !stall})
-			prefetch[SIZE - 1] <= fetch_data;
-		else if(!stall)
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			valid <= 0;
+			insn_pc <= 0;
 			prefetch[SIZE - 1] <= `NOP;
+		end else begin
+			insn_pc <= flush ? head : next_pc;
 
-		if(flush)
-			valid <= 0;
-		else if(fetched & ((stall & ~&valid) | ~|valid))
-			valid <= valid + 1;
-		else if(~stall & ~fetched & |valid)
-			valid <= valid - 1;
-	end
+			if(flush)
+				prefetch[SIZE - 1] <= `NOP;
+			else if(fetched && valid == SIZE - 1 + {{(ORDER - 1){1'b0}}, !stall})
+				prefetch[SIZE - 1] <= fetch_data;
+			else if(!stall)
+				prefetch[SIZE - 1] <= `NOP;
+
+			if(flush)
+				valid <= 0;
+			else if(fetched & ((stall & ~&valid) | ~|valid))
+				valid <= valid + 1;
+			else if(~stall & ~fetched & |valid)
+				valid <= valid - 1;
+		end
 
 	genvar i;
 	generate
 		for(i = 0; i < SIZE - 1; ++i) begin: prefetch_slots
-			always_ff @(posedge clk)
-				if(flush)
+			always_ff @(posedge clk or negedge rst_n)
+				if(!rst_n)
+					prefetch[i] <= `NOP;
+				else if(flush)
 					prefetch[i] <= `NOP;
 				else if(fetched & (~(|i | |valid) | (valid == i + {{(ORDER - 1){1'b0}}, ~stall})))
 					prefetch[i] <= fetch_data;
 				else if(~stall)
 					prefetch[i] <= prefetch[i + 1];
-
-			initial prefetch[i] = `NOP;
 		end
 	endgenerate
 
-	initial begin
-		insn_pc = 0;
-		valid = 0;
-		prefetch[SIZE - 1] = `NOP;
-	end
-
 endmodule