Implement psr read/write logic

3 files changed, 14 insertions, 8 deletions

diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv
index 7d666f3..f16db9a 100644
--- a/rtl/core/decode/decode.sv
+++ b/rtl/core/decode/decode.sv
@@ -27,6 +27,7 @@ module core_decode
 	assign dec.coproc = dec_coproc;
 
 	assign dec_ctrl.mul = mul;
+	assign dec_ctrl.psr = psr;
 	assign dec_ctrl.ldst = ldst;
 	assign dec_ctrl.branch = branch;
 	assign dec_ctrl.coproc = coproc;
@@ -35,7 +36,7 @@ module core_decode
 	assign dec_ctrl.undefined = undefined;
 	assign dec_ctrl.conditional = conditional;
 
-	assign dec_psr.saved = spsr;
+	assign dec_psr.saved = psr_saved;
 	assign dec_psr.write = psr_write;
 	assign dec_psr.wr_flags = psr_wr_flags;
 	assign dec_psr.wr_control = psr_wr_control;
@@ -43,8 +44,8 @@ module core_decode
 	assign dec_psr.restore_spsr = restore_spsr;
 
 	logic execute, undefined, conditional, writeback, update_flags,
-	      restore_spsr, branch, ldst, mul, coproc, spsr, psr_write,
-	      psr_wr_flags, psr_wr_control;
+	      restore_spsr, branch, ldst, mul, psr, coproc, psr_saved,
+	      psr_write, psr_wr_flags, psr_wr_control;
 
 	core_decode_mux mux
 	(
diff --git a/rtl/core/decode/isa.sv b/rtl/core/decode/isa.sv
index 4f2578d..1273a8b 100644
--- a/rtl/core/decode/isa.sv
+++ b/rtl/core/decode/isa.sv
@@ -194,7 +194,7 @@
 
 `define GROUP_MSR 28'b0_0_?_1_0_?_1_0_????_1111_0000_0000_????
 
-`define FIELD_MRS_R    [24]
+`define FIELD_MRS_R    [22]
 `define FIELD_MRS_RD   [15:12]
 `define FIELD_MSR_I    [25]
 `define FIELD_MSR_R    [22]
diff --git a/rtl/core/decode/mux.sv b/rtl/core/decode/mux.sv
index e8d930e..51fe14b 100644
--- a/rtl/core/decode/mux.sv
+++ b/rtl/core/decode/mux.sv
@@ -55,8 +55,9 @@ module core_decode_mux
 	                     branch,
 	                     ldst,
 	                     mul,
+	                     psr,
 	                     coproc,
-	                     spsr,
+	                     psr_saved,
 	                     psr_write,
 	                     psr_wr_flags,
 	                     psr_wr_control,
@@ -78,7 +79,8 @@ module core_decode_mux
 		conditional = 0;
 		restore_spsr = 0;
 
-		spsr = 0;
+		psr = 0;
+		psr_saved = 0;
 		psr_write = 0;
 		update_flags = 0;
 		psr_wr_flags = 1;
@@ -189,7 +191,8 @@ module core_decode_mux
 				dec_data.rd = mrs_rd;
 				dec_data.uses_rn = 0;
 
-				spsr = mrs_spsr;
+				psr = 1;
+				psr_saved = mrs_spsr;
 				writeback = 1;
 				conditional = 1;
 			end
@@ -201,9 +204,10 @@ module core_decode_mux
 				snd_ror_if_imm = 1;
 				snd_shift_by_reg_if_reg = 0;
 
-				spsr = msr_spsr;
+				psr = 1;
 				dec_snd = snd;
 				psr_write = 1;
+				psr_saved = msr_spsr;
 				conditional = 1;
 				psr_wr_flags = msr_fields.f;
 				psr_wr_control = msr_fields.c;
@@ -233,6 +237,7 @@ module core_decode_mux
 			execute = 0;
 
 			mul = 1'bx;
+			psr = 1'bx;
 			ldst = 1'bx;
 			branch = 1'bx;
 			coproc = 1'bx;