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| author | Alejandro Soto <alejandro@34project.org> | 2022-09-25 20:05:30 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-09-25 20:05:30 -0600 |
| commit | 146586c0fb52dccb9ab483b8b20369ed19ae5116 (patch) | |
| tree | 144e3ac13ecb95f164ab47cc4e7f936cf52da087 /rtl/core/cycles.sv | |
| parent | fa370016708149976c748c14eadad1f89cf5a8ea (diff) | |
Implement flag updates
Diffstat (limited to 'rtl/core/cycles.sv')
| -rw-r--r-- | rtl/core/cycles.sv | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv index 0f6ce15..726a40a 100644 --- a/rtl/core/cycles.sv +++ b/rtl/core/cycles.sv @@ -4,8 +4,9 @@ module core_cycles ( input logic clk, decode_execute, - decode_writeback, decode_branch, + decode_writeback, + decode_update_flags, input reg_num decode_rd, input ptr decode_branch_offset, input alu_op decode_data_op, @@ -14,6 +15,7 @@ module core_cycles output logic stall, branch, writeback, + update_flags, output reg_num rd, output ptr branch_target, pc, @@ -38,6 +40,7 @@ module core_cycles if(next_cycle == EXECUTE) begin branch <= 0; writeback <= 0; + update_flags <= 0; branch_target <= 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; if(decode_execute) begin @@ -49,6 +52,7 @@ module core_cycles pc <= fetch_insn_pc; rd <= decode_rd; data_op <= decode_data_op; + update_flags <= decode_update_flags; end end |