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authorAlejandro Soto <alejandro@34project.org>2022-09-26 10:30:10 -0600
committerAlejandro Soto <alejandro@34project.org>2022-09-26 10:30:10 -0600
commit00398c1b7c30830adf476ae3eb9f37dc76db049f (patch)
tree0794a6a6cc0fb00c22c3bffd0a8594804baf8dd0 /rtl/core/cycles.sv
parent6270090795a2897517dd435afcaa9eec9f74e027 (diff)
Fix writeback timing
Diffstat (limited to 'rtl/core/cycles.sv')
-rw-r--r--rtl/core/cycles.sv9
1 files changed, 4 insertions, 5 deletions
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
index f503188..1524883 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/cycles.sv
@@ -72,13 +72,13 @@ module core_cycles
unique case(next_cycle)
EXECUTE: begin
branch <= 0;
- writeback <= 0;
update_flags <= 0;
branch_target <= 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
+ final_writeback <= 0;
if(dec_execute) begin
branch <= dec_branch;
- writeback <= dec_writeback & ~dec_alu.snd_shift_by_reg;
+ final_writeback <= dec_writeback;
update_flags <= dec_update_flags;
branch_target <= pc_visible + dec_branch_offset;
@@ -98,10 +98,9 @@ module core_cycles
ra <= dec_alu.rn;
rb <= dec_alu.r_snd;
r_shift <= dec_alu.r_shift;
-
- final_writeback <= dec_writeback;
end
+ writeback <= final_writeback;
pc <= fetch_insn_pc;
end
@@ -109,7 +108,7 @@ module core_cycles
rb <= r_shift;
data_snd_shift_by_reg <= 0;
saved_base <= rd_value_b;
- writeback <= final_writeback;
+ writeback <= 0;
end
endcase
end