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authorAlejandro Soto <alejandro@34project.org>2022-09-25 20:06:29 -0600
committerAlejandro Soto <alejandro@34project.org>2022-09-25 20:06:29 -0600
commitbd8f26b888ec30aac61586f4165681ad41046cc4 (patch)
treed5bf6bbaffc5e2912b360bf08511d78f9af6aa3c /rtl/core/cycles.sv
parent146586c0fb52dccb9ab483b8b20369ed19ae5116 (diff)
Shorten decode_* nets to dec_*
Diffstat (limited to '')
-rw-r--r--rtl/core/cycles.sv28
1 files changed, 14 insertions, 14 deletions
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
index 726a40a..3520467 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/cycles.sv
@@ -3,13 +3,13 @@
module core_cycles
(
input logic clk,
- decode_execute,
- decode_branch,
- decode_writeback,
- decode_update_flags,
- input reg_num decode_rd,
- input ptr decode_branch_offset,
- input alu_op decode_data_op,
+ dec_execute,
+ dec_branch,
+ dec_writeback,
+ dec_update_flags,
+ input reg_num dec_rd,
+ input ptr dec_branch_offset,
+ input alu_op dec_data_op,
input ptr fetch_insn_pc,
output logic stall,
@@ -43,16 +43,16 @@ module core_cycles
update_flags <= 0;
branch_target <= 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx;
- if(decode_execute) begin
- branch <= decode_branch;
- writeback <= decode_writeback;
- branch_target <= pc_visible + decode_branch_offset;
+ if(dec_execute) begin
+ branch <= dec_branch;
+ writeback <= dec_writeback;
+ branch_target <= pc_visible + dec_branch_offset;
end
pc <= fetch_insn_pc;
- rd <= decode_rd;
- data_op <= decode_data_op;
- update_flags <= decode_update_flags;
+ rd <= dec_rd;
+ data_op <= dec_data_op;
+ update_flags <= dec_update_flags;
end
end