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| author | Alejandro Soto <alejandro@34project.org> | 2022-10-16 01:38:33 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-16 01:38:33 -0600 |
| commit | 2e6ce7931b690ccec1e41fa6847dfc1351c59d75 (patch) | |
| tree | 81759ffd1e61465a26e03414f25fbbb918308350 /rtl/core/cycles.sv | |
| parent | f0b38daac3a2f987deb79fcca763f3b84b0f2b73 (diff) | |
Rename cycles as control
Diffstat (limited to '')
| -rw-r--r-- | rtl/core/control/control.sv (renamed from rtl/core/cycles.sv) | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/rtl/core/cycles.sv b/rtl/core/control/control.sv index ad35762..398c8c7 100644 --- a/rtl/core/cycles.sv +++ b/rtl/core/control/control.sv @@ -1,6 +1,6 @@ `include "core/uarch.sv" -module core_cycles +module core_control ( input logic clk, dec_execute, @@ -76,7 +76,7 @@ module core_cycles ((dec_update_flags || dec_conditional) && (final_update_flags || update_flags)) || (final_writeback && (final_rd == dec_data.rn || final_rd == dec_snd.r)); - core_cycles_ldst_pop ldst_pop + core_control_ldst_pop ldst_pop ( .regs(mem_regs), .valid(pop_valid), @@ -171,7 +171,6 @@ module core_cycles data_imm <= dec_snd.imm; data_shift_imm <= dec_snd.shift_imm; - shifter.shl <= dec_snd.shl; shifter.shr <= dec_snd.shr; shifter.ror <= dec_snd.ror; shifter.put_carry <= dec_snd.put_carry; |