Expose cp15 signals to core toplevel

3 files changed, 15 insertions, 9 deletions

diff --git a/rtl/core/cp15/cp15.sv b/rtl/core/cp15/cp15.sv
index f924c21..8ddc474 100644
--- a/rtl/core/cp15/cp15.sv
+++ b/rtl/core/cp15/cp15.sv
@@ -1,5 +1,6 @@
-`include "core/uarch.sv"
 `include "core/cp15/map.sv"
+`include "core/mmu/format.sv"
+`include "core/uarch.sv"
 
 module core_cp15
 (
@@ -9,7 +10,10 @@ module core_cp15
 	input  coproc_decode dec,
 	input  word          write,
 
-	output word          read
+	output word          read,
+	output logic         high_vectors,
+	                     mmu_enable,
+	output mmu_base      mmu_ttbr
 );
 
 	logic load;
diff --git a/rtl/core/cp15/syscfg.sv b/rtl/core/cp15/syscfg.sv
index 599b682..d75f7ac 100644
--- a/rtl/core/cp15/syscfg.sv
+++ b/rtl/core/cp15/syscfg.sv
@@ -11,10 +11,12 @@ module core_cp15_syscfg
 	input  cp_opcode op2,
 	input  word      write,
 
-	output word      read
+	output word      read,
+	output logic     high_vectors,
+	                 mmu_enable
 );
 
-	logic mmu_enable, dcache_enable, icache_enable, high_vectors;
+	logic dcache_enable, icache_enable;
 
 	cp15_syscfg_ctrl ctrl, write_ctrl;
 
diff --git a/rtl/core/cp15/ttbr.sv b/rtl/core/cp15/ttbr.sv
index 622dd3f..5162edb 100644
--- a/rtl/core/cp15/ttbr.sv
+++ b/rtl/core/cp15/ttbr.sv
@@ -11,11 +11,11 @@ module core_cp15_ttbr
 	                 transfer,
 	input  word      write,
 
-	output word      read
+	output word      read,
+	output mmu_base  mmu_ttbr
 );
 
 	logic s, c;
-	mmu_base base;
 	cp15_ttbr read_ttbr, write_ttbr;
 	logic[1:0] rgn;
 
@@ -27,19 +27,19 @@ module core_cp15_ttbr
 	assign read_ttbr.sbz = 9'd0;
 	assign read_ttbr.rgn = rgn;
 	assign read_ttbr.imp = 0;
-	assign read_ttbr.base = base;
+	assign read_ttbr.base = mmu_ttbr;
 
 	always @(posedge clk or negedge rst_n)
 		if(!rst_n) begin
 			s <= 0;
 			c <= 0;
 			rgn <= 0;
-			base <= 0;
+			mmu_ttbr <= 0;
 		end else if(transfer && !load) begin
 			s <= write_ttbr.s;
 			c <= write_ttbr.c;
 			rgn <= write_ttbr.rgn;
-			base <= write_ttbr.base;
+			mmu_ttbr <= write_ttbr.base;
 		end
 
 endmodule