Implement CP15 ID register

2 files changed, 122 insertions, 7 deletions

diff --git a/rtl/core/cp15/cpuid.sv b/rtl/core/cp15/cpuid.sv
index fd24631..c9cab59 100644
--- a/rtl/core/cp15/cpuid.sv
+++ b/rtl/core/cp15/cpuid.sv
@@ -3,16 +3,68 @@
 
 module core_cp15_cpuid
 (
-	output word read
+	input  cp_opcode op2,
+	output word      read
 );
 
-	/* If an <opcode2> value corresponding to an unimplemented or
-	 * reserved ID register is encountered, the System Control
-	 * coprocessor returns the value of the main ID register.
-	 *
-	 * ARM810.pdf, p. 104: Reading from CP15 register 0 returns
+	/* ARM810.pdf, p. 104: Reading from CP15 register 0 returns
 	 * the value 0x4101810x.
 	 */
-	assign read = 32'h41018100;
+	cp15_cpuid_main main;
+	assign main.implementor = 8'h41; // 'A' (ARM)
+	assign main.variant = 4'h0;
+	assign main.architecture = 4'h1; // ARMv4 (no Thumb)
+	assign main.part_number = 12'h810;
+	assign main.revision = 4'h0;
+
+	cp15_cpuid_cache cache;
+	assign cache.mbz = 3'b000;
+	assign cache.ctype = 4'b0001; // Write-back, range ops not supported
+	assign cache.s = 1;           // Split instruction and data caches
+	assign cache.dsize = cachesize;
+	assign cache.isize = cachesize;
+
+	cp15_cpuid_cache_size cachesize;
+	assign cachesize.p = 0;
+	assign cachesize.mbz = 0;
+	assign cachesize.size = 4'b0100; // 8KiB
+	assign cachesize.assoc = 3'b001; // 2-way associative
+	assign cachesize.m = 0;
+	assign cachesize.len = 2'b10;    // 32-byte cache lines
+
+	cp15_cpuid_tcm tcm;
+	assign tcm = 0;
+
+	cp15_cpuid_tlb tlb;
+	assign tlb.sbz0 = 8'd0;
+	assign tlb.ilsize = 8'd0;
+	assign tlb.dlsize = 8'd0;
+	assign tlb.sbz1 = 7'd0;
+	assign tlb.s = 1;
+
+	cp15_cpuid_mpu mpu;
+	assign mpu = 0;
+
+	always_comb
+		unique case(op2)
+			`CP15_CPUID_CACHE:
+				read = cache;
+
+			`CP15_CPUID_TCM:
+				read = tcm;
+
+			`CP15_CPUID_TLB:
+				read = tlb;
+
+			`CP15_CPUID_MPU:
+				read = mpu;
+
+			/* If an <opcode2> value corresponding to an unimplemented or
+			 * reserved ID register is encountered, the System Control
+			 * coprocessor returns the value of the main ID register.
+			 */
+			default:
+				read = main;
+		endcase
 
 endmodule
diff --git a/rtl/core/cp15/map.sv b/rtl/core/cp15/map.sv
index 0c0add5..1f8c58f 100644
--- a/rtl/core/cp15/map.sv
+++ b/rtl/core/cp15/map.sv
@@ -14,4 +14,67 @@
 `define CP15_CRN_DMA       4'd11
 `define CP15_CRN_PID       4'd13
 
+typedef struct packed
+{
+	logic[31:24] implementor;
+	logic[23:20] variant;
+	logic[19:16] architecture;
+	logic[15:4]  part_number;
+	logic[3:0]   revision;
+} cp15_cpuid_main;
+
+`define CP15_CPUID_CACHE 3'b001
+
+typedef struct packed
+{
+	logic[11:11] p;
+	logic[10:10] mbz;
+	logic[9:6]   size;
+	logic[5:3]   assoc;
+	logic[2:2]   m;
+	logic[1:0]   len;
+} cp15_cpuid_cache_size;
+
+typedef struct packed
+{
+	logic[31:29]          mbz;
+	logic[28:25]          ctype;
+	logic[24:24]          s;
+	cp15_cpuid_cache_size dsize,
+	                      isize;
+} cp15_cpuid_cache;
+
+`define CP15_CPUID_TCM 3'b010
+
+typedef struct packed
+{
+	logic[31:29] mbz;
+	logic[28:19] sbz0;
+	logic[18:16] dtcm;
+	logic[15:3]  sbz1;
+	logic[2:0]   itcm;
+} cp15_cpuid_tcm;
+
+`define CP15_CPUID_TLB 3'b011
+
+typedef struct packed
+{
+	logic[31:24] sbz0;
+	logic[23:16] ilsize;
+	logic[15:8]  dlsize;
+	logic[7:1]   sbz1;
+	logic[0:0]   s;
+} cp15_cpuid_tlb;
+
+`define CP15_CPUID_MPU 3'b100
+
+typedef struct packed
+{
+	logic[31:24] sbz0;
+	logic[23:16] iregion;
+	logic[15:8]  dregion;
+	logic[7:1]   sbz1;
+	logic[0:0]   s;
+} cp15_cpuid_mpu;
+
 `endif