summaryrefslogtreecommitdiff
path: root/rtl/core/cp15/cpuid.sv
diff options
context:
space:
mode:
authorAlejandro Soto <alejandro@34project.org>2022-11-01 23:00:52 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-01 23:04:24 -0600
commited42ddad4a09ef6919ac3c1ee54ad17f4e8b13bc (patch)
tree8f7f523e8f1e5857769b9bb2f34931d3bb5cc9d0 /rtl/core/cp15/cpuid.sv
parent45efe8bf6148d9d1cd7127a5d245d5e3cd6b4647 (diff)
Add CPUID register
Diffstat (limited to '')
-rw-r--r--rtl/core/cp15/cpuid.sv18
1 files changed, 18 insertions, 0 deletions
diff --git a/rtl/core/cp15/cpuid.sv b/rtl/core/cp15/cpuid.sv
new file mode 100644
index 0000000..fd24631
--- /dev/null
+++ b/rtl/core/cp15/cpuid.sv
@@ -0,0 +1,18 @@
+`include "core/uarch.sv"
+`include "core/cp15/map.sv"
+
+module core_cp15_cpuid
+(
+ output word read
+);
+
+ /* If an <opcode2> value corresponding to an unimplemented or
+ * reserved ID register is encountered, the System Control
+ * coprocessor returns the value of the main ID register.
+ *
+ * ARM810.pdf, p. 104: Reading from CP15 register 0 returns
+ * the value 0x4101810x.
+ */
+ assign read = 32'h41018100;
+
+endmodule