diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-08 13:00:40 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-08 13:29:23 -0600 |
| commit | f6929f9a4703e3eee9d7bd9752de055729cdd498 (patch) | |
| tree | 770acb4f96fd16e0f12bec2c5ed5cfdfa5a4c315 /rtl/core/control | |
| parent | 89a8edd4bb96787c69118dd5f549345015b2d480 (diff) | |
Register decode output in a new porch stage
Diffstat (limited to 'rtl/core/control')
| -rw-r--r-- | rtl/core/control/control.sv | 2 | ||||
| -rw-r--r-- | rtl/core/control/issue.sv | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 4ea590a..077ba1c 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -4,7 +4,7 @@ module core_control ( input logic clk, input insn_decode dec, - input ptr fetch_insn_pc, + input ptr insn_pc, input psr_flags flags, alu_flags, input word rd_value_a, diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index 5ed03f0..e3644c4 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -5,7 +5,7 @@ module core_control_issue input logic clk, input insn_decode dec, - input ptr fetch_insn_pc, + input ptr insn_pc, input ctrl_cycle next_cycle, input logic next_bubble, @@ -22,7 +22,7 @@ module core_control_issue ); assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble; - assign next_pc_visible = fetch_insn_pc + 2; + assign next_pc_visible = insn_pc + 2; always_ff @(posedge clk) if(next_cycle == ISSUE) begin @@ -30,10 +30,10 @@ module core_control_issue `ifdef VERILATOR if(dec.ctrl.undefined) - $display("[core] undefined insn: [0x%08x] %08x", fetch_insn_pc << 2, insn); + $display("[core] undefined insn: [0x%08x] %08x", insn_pc << 2, insn); `endif - pc <= fetch_insn_pc; + pc <= insn_pc; pc_visible <= next_pc_visible; end |