Simplify flags datapath

3 files changed, 9 insertions, 23 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 4bff86e..82aad33 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -37,7 +37,6 @@ module core_control
 	output ptr             branch_target,
 	                       pc_visible,
 	output psr_mode        reg_mode,
-	output psr_flags       wb_alu_flags,
 	output alu_op          alu,
 	output word            alu_a,
 	                       alu_b,
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index d590325..d2c4de8 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -10,9 +10,7 @@ module core_control_stall
 
 	input  ctrl_cycle  next_cycle,
 	input  logic       final_update_flags,
-	                   update_flags,
 	                   final_writeback,
-	                   writeback,
 	input  reg_num     final_rd,
 
 	output logic       halted,
@@ -21,8 +19,7 @@ module core_control_stall
 	                   next_bubble
 );
 
-	logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard,
-		  flags_hazard, flags_dependency, updating_flags;
+	logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, flags_hazard;
 
 	assign stall = !next_cycle.issue || next_bubble || halt;
 	assign halted = halt && !next_bubble;
@@ -32,13 +29,9 @@ module core_control_stall
 	assign pc_rd_hazard = final_writeback && (rn_pc_hazard || snd_pc_hazard);
 	assign pc_wr_hazard = final_writeback && final_rd == `R15;
 	assign rn_pc_hazard = dec.data.uses_rn && dec.data.rn == `R15;
+	assign flags_hazard = dec.ctrl.conditional && final_update_flags;
 	assign snd_pc_hazard = !dec.snd.is_imm && dec.snd.r == `R15;
 
-	assign flags_hazard = flags_dependency && updating_flags;
-
-	assign updating_flags = final_update_flags || update_flags;
-	assign flags_dependency = dec.psr.update_flags || dec.ctrl.conditional;
-
 	always_ff @(posedge clk or negedge rst_n)
 		bubble <= !rst_n ? 0 : next_cycle.issue && next_bubble;
 
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 5d6d7c6..f28e9a9 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -31,8 +31,7 @@ module core_control_writeback
 	                   final_writeback,
 	                   update_flags,
 	                   final_update_flags,
-	output word        wr_value,
-	output psr_flags   wb_alu_flags
+	output word        wr_value
 );
 
 	reg_num last_rd;
@@ -79,6 +78,12 @@ module core_control_writeback
 			wr_value = vector;
 		else if(next_cycle.mul_hi_wb)
 			wr_value = mul_q_hi;
+
+		update_flags = 0;
+		if(next_cycle.issue)
+			update_flags = final_update_flags;
+		else if(next_cycle.exception)
+			update_flags = 0;
 	end
 
 	always_ff @(posedge clk or negedge rst_n)
@@ -86,14 +91,9 @@ module core_control_writeback
 			last_rd <= 0;
 			final_rd <= 0;
 			final_writeback <= 0;
-
-			update_flags <= 0;
 			final_update_flags <= 0;
-
-			wb_alu_flags <= {$bits(wb_alu_flags){1'b0}};
 		end else begin
 			last_rd <= rd;
-			wb_alu_flags <= alu_flags;
 
 			if(next_cycle.issue)
 				final_rd <= dec.data.rd;
@@ -110,12 +110,6 @@ module core_control_writeback
 			else if(next_cycle.exception)
 				final_writeback <= 1;
 
-			update_flags <= 0;
-			if(next_cycle.issue)
-				update_flags <= final_update_flags;
-			else if(next_cycle.exception)
-				update_flags <= 0;
-
 			if(next_cycle.issue)
 				final_update_flags <= issue && dec.psr.update_flags;
 			else if(next_cycle.exception)