Add PSR control signal set

3 files changed, 5 insertions, 2 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 056606d..917dbf8 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -4,6 +4,7 @@ module core_control
 (
 	input  logic           clk,
 	input  datapath_decode dec,
+	input  psr_decode      dec_psr,
 	input  branch_decode   dec_branch,
 	input  data_decode     dec_data,
 	input  snd_decode      dec_snd,
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index 5ac1c7a..edf9265 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -5,6 +5,7 @@ module core_control_stall
 	input  logic           clk,
 
 	input  datapath_decode dec,
+	input  psr_decode      dec_psr,
 	input  data_decode     dec_data,
 	input  snd_decode      dec_snd,
 
@@ -32,7 +33,7 @@ module core_control_stall
 	assign rn_hazard = dec_data.uses_rn && (final_rd == dec_data.rn || dec_data.rn == `R15);
 	assign snd_hazard = !dec_snd.is_imm && (dec_snd.r == final_rd || dec_snd.r == `R15);
 
-	assign flags_dependency = dec.update_flags || dec.conditional;
+	assign flags_dependency = dec_psr.update_flags || dec.conditional;
 	assign updating_flags = final_update_flags || update_flags;
 
 	always_ff @(posedge clk)
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv
index 15b17ee..85b2f9f 100644
--- a/rtl/core/control/writeback.sv
+++ b/rtl/core/control/writeback.sv
@@ -5,6 +5,7 @@ module core_control_writeback
 	input  logic           clk,
 
 	input  datapath_decode dec,
+	input  psr_decode      dec_psr,
 	input  data_decode     dec_data,
 
 	input  ctrl_cycle      cycle,
@@ -102,7 +103,7 @@ module core_control_writeback
 
 		unique0 case(next_cycle)
 			ISSUE:
-				final_update_flags <= issue && dec.update_flags;
+				final_update_flags <= issue && dec_psr.update_flags;
 
 			EXCEPTION:
 				final_update_flags <= 0;