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| author | Alejandro Soto <alejandro@34project.org> | 2022-10-17 01:03:25 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-10-17 01:03:25 -0600 |
| commit | 5079281c8e8889efc2eeba664d93644126006743 (patch) | |
| tree | 7d02022f71cd860caaae9d63f280d19f2d92ddab /rtl/core/control | |
| parent | 87c73314d7ce0062b13ae14f376ec50a4653fb18 (diff) | |
Fix data hazards in nzcv and PC increment
Diffstat (limited to 'rtl/core/control')
| -rw-r--r-- | rtl/core/control/control.sv | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 398c8c7..653d896 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -14,6 +14,7 @@ module core_control input ldst_decode dec_ldst, input ptr fetch_insn_pc, input psr_flags flags, + alu_flags, input word rd_value_a, rd_value_b, q_alu, @@ -33,6 +34,7 @@ module core_control output ptr branch_target, pc_visible, output psr_mode reg_mode, + output psr_flags wb_alu_flags, output alu_op alu, output word alu_a, alu_b, @@ -195,6 +197,7 @@ module core_control final_update_flags <= dec_update_flags; end + wb_alu_flags <= alu_flags; update_flags <= final_update_flags; writeback <= final_writeback; rd <= final_rd; @@ -261,6 +264,8 @@ module core_control branch_target = 30'd0; data_snd_shift_by_reg = 0; + wb_alu_flags = 4'b0000; + ldst = 0; ldst_pre = 0; ldst_writeback = 0; |
