rtl: implement exclusive monitor datapath

2 files changed, 7 insertions, 0 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index ed0a1e1..6090f2d 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -25,6 +25,7 @@ module core_control
 	input  logic           c_shifter,
 	                       mem_ready,
 	                       mem_fault,
+	                       mem_ex_fail,
 	input  word            mem_data_rd,
 	input  logic           mul_ready,
 	input  word            mul_q_hi,
@@ -62,6 +63,7 @@ module core_control
 	output logic[3:0]      mem_data_be,
 	output logic           mem_start,
 	                       mem_write,
+	                       mem_ex_lock,
 	                       mem_user,
 	output word            mul_a,
 	                       mul_b,
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index bb057bb..0e0a39c 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -8,6 +8,7 @@ module core_control_ldst
 	input  insn_decode dec,
 	input  logic       issue,
 	                   mem_ready,
+	                   mem_ex_fail,
 	input  word        rd_value_b,
 	                   q_alu,
 	                   q_shifter,
@@ -23,6 +24,7 @@ module core_control_ldst
 	                   mem_offset,
 	output logic       mem_start,
 	                   mem_write,
+	                   mem_ex_lock,
 	                   mem_user,
 	                   pop_valid,
 	                   ldst,
@@ -43,6 +45,9 @@ module core_control_ldst
 	assign ldst_next = !cycle.transfer || mem_ready;
 	assign mem_data_wr = q_shifter;
 
+	//TODO
+	assign mem_ex_lock = 0;
+
 	core_control_ldst_pop pop
 	(
 		.regs(mem_regs),