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authorAlejandro Soto <alejandro@34project.org>2022-12-15 12:30:30 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-16 16:29:10 -0600
commit6e52e1df7567cdf419a193bf541dd98c0253e5a4 (patch)
tree6acffed0adfc18a4d3b0de3a4250eca11c644649 /rtl/core/control
parent7bf965b755b667f7da05e0995c2f09c54a8a2f11 (diff)
Add interrupt controller to Platform Designer
Diffstat (limited to '')
-rw-r--r--rtl/core/control/exception.sv11
1 files changed, 5 insertions, 6 deletions
diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv
index 21adb19..ed7893e 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/control/exception.sv
@@ -29,14 +29,14 @@ module core_control_exception
assign exception = undefined || syscall || prefetch_abort || mem_fault || pending_irq;
assign exception_vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00};
- always @(posedge clk or negedge rst_n) begin
+ always @(posedge clk or negedge rst_n)
if(!rst_n) begin
syscall <= 0;
pending_irq <= 0;
vector_offset <= 0;
exception_mode <= 0;
exception_offset_pc <= 0;
- end begin
+ end else begin
if(next_cycle.issue) begin
syscall <= issue && dec.ctrl.swi;
pending_irq <= issue && irq && !intmask.i;
@@ -59,10 +59,9 @@ module core_control_exception
vector_offset <= 3'b010;
exception_mode <= `MODE_SVC;
end
- end
- if(next_cycle.escalate)
- exception_offset_pc <= !mem_fault;
- end
+ if(next_cycle.escalate)
+ exception_offset_pc <= !mem_fault;
+ end
endmodule