Expose cp15 signals to core toplevel

2 files changed, 2 insertions, 5 deletions

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 79d6d36..3c55507 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -25,6 +25,7 @@ module core_control
 	input  word            mul_q_hi,
 	                       mul_q_lo,
 	                       coproc_read,
+	input  logic           high_vectors,
 
 `ifdef VERILATOR
 	input  word            insn,
diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv
index c4f3772..3965114 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/control/exception.sv
@@ -6,24 +6,20 @@ module core_control_exception
 	             rst_n,
 
 	input  logic undefined,
+	             high_vectors,
 
 	output word  vector,
 	output logic exception
 );
 
-	logic high_vectors;
 	logic[2:0] vector_offset;
 
 	assign exception = undefined; //TODO
-	assign high_vectors = 0; //TODO
 	assign vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00};
 
 	always_comb
 		vector_offset = 3'b001; //TODO
 
-	//TODO: spsr_<mode> = cpsr
-	//TODO: actualizar modo
-	//TODO: deshabilitar IRQs/FIQs dependiendo de modo
 	//TODO: Considerar que data abort usa + 8, no + 4
 
 endmodule