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authorAlejandro Soto <alejandro@34project.org>2022-12-18 13:19:55 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-18 13:19:55 -0600
commit46eae9622ab6f1a39c6253dc0998e03c57513510 (patch)
treef9eb98da738e00f16bf7493ea9a4061dec9645f9 /rtl/core/control
parent6d458ad9629268ecfc69881b4fb10dca0498fbd0 (diff)
Implement mode-translated memory accesses
Diffstat (limited to '')
-rw-r--r--rtl/core/control/control.sv1
-rw-r--r--rtl/core/control/ldst/ldst.sv7
2 files changed, 6 insertions, 2 deletions
diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index a421572..cab47ce 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -61,6 +61,7 @@ module core_control
output logic[3:0] mem_data_be,
output logic mem_start,
mem_write,
+ mem_user,
output word mul_a,
mul_b,
mul_c_hi,
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index c8f0dcb..bb057bb 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -23,6 +23,7 @@ module core_control_ldst
mem_offset,
output logic mem_start,
mem_write,
+ mem_user,
pop_valid,
ldst,
ldst_next,
@@ -73,6 +74,7 @@ module core_control_ldst
base <= {$bits(base){1'b0}};
mem_regs <= {$bits(mem_regs){1'b0}};
+ mem_user <= 0;
mem_write <= 0;
mem_start <= 0;
mem_offset <= 0;
@@ -81,9 +83,10 @@ module core_control_ldst
mem_start <= 0;
if(next_cycle.issue) begin
- // TODO: dec.ldst.unprivileged
- if(issue)
+ if(issue) begin
ldst <= dec.ctrl.ldst;
+ mem_user <= dec.ldst.unprivileged;
+ end
pre <= dec.ldst.pre_indexed;
size <= dec.ldst.size;