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| author | Alejandro Soto <alejandro@34project.org> | 2023-10-03 07:44:27 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2023-10-03 07:44:27 -0600 |
| commit | 6ddd97b7289b043c41ac65ae35931bd5b5acfaeb (patch) | |
| tree | f03430dedaae6e02352e74d35d8daed174be6031 /rtl/core/control/writeback.sv | |
| parent | 548187dfc392d0beef4cc86e7d3d22d885276e5d (diff) | |
rtl/core/control: reject strex after exceptions
Diffstat (limited to 'rtl/core/control/writeback.sv')
| -rw-r--r-- | rtl/core/control/writeback.sv | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 50e780d..027a7d7 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -10,11 +10,11 @@ module core_control_writeback input word q_alu, ldst_read, input logic mem_ready, - mem_ex_fail, mem_ex_lock, mem_write, input word mul_q_hi, mul_q_lo, + strex_ok, input ctrl_cycle cycle, next_cycle, @@ -28,6 +28,7 @@ module core_control_writeback input logic issue, pop_valid, ldst_next, + ldst_reject, output reg_num rd, final_rd, @@ -64,7 +65,7 @@ module core_control_writeback writeback = 0; if(cycle.transfer) - wr_value = (mem_ex_lock && mem_write) ? {31'd0, mem_ex_fail} : ldst_read; + wr_value = (mem_ex_lock && mem_write) ? strex_ok : ldst_read; else if(cycle.base_writeback) wr_value = saved_base; else if(cycle.mul || cycle.mul_hi_wb) |