diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-15 20:02:17 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-15 20:56:48 -0600 |
| commit | 2b457b34b842e0e2fa6236b304860ad3ba474b16 (patch) | |
| tree | 6068a578722ae89a453e504db6b6c3688dea1d30 /rtl/core/control/writeback.sv | |
| parent | a055bc85bc50897644e7ed62699abff46d818d5f (diff) | |
Implement sub-word memory accesses
Diffstat (limited to 'rtl/core/control/writeback.sv')
| -rw-r--r-- | rtl/core/control/writeback.sv | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/rtl/core/control/writeback.sv b/rtl/core/control/writeback.sv index 914236c..24b3ed5 100644 --- a/rtl/core/control/writeback.sv +++ b/rtl/core/control/writeback.sv @@ -8,7 +8,7 @@ module core_control_writeback input insn_decode dec, input psr_flags alu_flags, input word q_alu, - mem_data_rd, + ldst_read, input logic mem_ready, mem_write, input word mul_q_hi, @@ -61,7 +61,7 @@ module core_control_writeback writeback = 0; if(cycle.transfer) - wr_value = mem_data_rd; + wr_value = ldst_read; else if(cycle.base_writeback) wr_value = saved_base; else if(cycle.mul || cycle.mul_hi_wb) @@ -72,9 +72,9 @@ module core_control_writeback if(next_cycle.transfer) begin if(mem_ready) - wr_value = mem_data_rd; + wr_value = ldst_read; end else if(next_cycle.base_writeback) - wr_value = mem_data_rd; + wr_value = ldst_read; else if(next_cycle.exception) wr_value = vector; else if(next_cycle.mul_hi_wb) |