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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-09 09:25:48 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-09 09:25:48 -0600 |
| commit | 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 (patch) | |
| tree | a04fff74505af30c8044f80f523fd887331e6234 /rtl/core/control/stall.sv | |
| parent | 65590be80332d132d7037bfe3bb19e5d6e5bcd7b (diff) | |
Implement reset
Diffstat (limited to 'rtl/core/control/stall.sv')
| -rw-r--r-- | rtl/core/control/stall.sv | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv index 223fecb..60dfbbe 100644 --- a/rtl/core/control/stall.sv +++ b/rtl/core/control/stall.sv @@ -3,6 +3,7 @@ module core_control_stall ( input logic clk, + rst_n, input insn_decode dec, @@ -33,10 +34,7 @@ module core_control_stall assign flags_dependency = dec.psr.update_flags || dec.ctrl.conditional; assign updating_flags = final_update_flags || update_flags; - always_ff @(posedge clk) - bubble <= next_cycle == ISSUE && next_bubble; - - initial - bubble = 0; + always_ff @(posedge clk or negedge rst_n) + bubble <= !rst_n ? 0 : next_cycle == ISSUE && next_bubble; endmodule |
