Implement psr read/write logic

1 files changed, 5 insertions, 2 deletions

diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index d2c4de8..085f11e 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -10,6 +10,8 @@ module core_control_stall
 
 	input  ctrl_cycle  next_cycle,
 	input  logic       final_update_flags,
+	                   final_restore_spsr,
+	                   final_psr_write,
 	                   final_writeback,
 	input  reg_num     final_rd,
 
@@ -19,13 +21,14 @@ module core_control_stall
 	                   next_bubble
 );
 
-	logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, flags_hazard;
+	logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, psr_hazard, flags_hazard;
 
 	assign stall = !next_cycle.issue || next_bubble || halt;
 	assign halted = halt && !next_bubble;
-	assign next_bubble = pc_rd_hazard || pc_wr_hazard || flags_hazard;
+	assign next_bubble = pc_rd_hazard || pc_wr_hazard || flags_hazard || psr_hazard;
 
 	//FIXME: pc_rd_hazard no debería definirse sin final_writeback?
+	assign psr_hazard = final_psr_write || final_restore_spsr;
 	assign pc_rd_hazard = final_writeback && (rn_pc_hazard || snd_pc_hazard);
 	assign pc_wr_hazard = final_writeback && final_rd == `R15;
 	assign rn_pc_hazard = dec.data.uses_rn && dec.data.rn == `R15;