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authorAlejandro Soto <alejandro@34project.org>2022-11-16 14:08:16 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-16 14:08:16 -0600
commit8c410eab0ea97b737ecd59cd4a1f7582f8c045cf (patch)
tree38ea02af4ec12abf77bb852025244e40129f59fa /rtl/core/control/stall.sv
parenta94c52d5117645016ee319abc30c92f137a4b17e (diff)
Simplify flags datapath
Diffstat (limited to '')
-rw-r--r--rtl/core/control/stall.sv11
1 files changed, 2 insertions, 9 deletions
diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv
index d590325..d2c4de8 100644
--- a/rtl/core/control/stall.sv
+++ b/rtl/core/control/stall.sv
@@ -10,9 +10,7 @@ module core_control_stall
input ctrl_cycle next_cycle,
input logic final_update_flags,
- update_flags,
final_writeback,
- writeback,
input reg_num final_rd,
output logic halted,
@@ -21,8 +19,7 @@ module core_control_stall
next_bubble
);
- logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard,
- flags_hazard, flags_dependency, updating_flags;
+ logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, flags_hazard;
assign stall = !next_cycle.issue || next_bubble || halt;
assign halted = halt && !next_bubble;
@@ -32,13 +29,9 @@ module core_control_stall
assign pc_rd_hazard = final_writeback && (rn_pc_hazard || snd_pc_hazard);
assign pc_wr_hazard = final_writeback && final_rd == `R15;
assign rn_pc_hazard = dec.data.uses_rn && dec.data.rn == `R15;
+ assign flags_hazard = dec.ctrl.conditional && final_update_flags;
assign snd_pc_hazard = !dec.snd.is_imm && dec.snd.r == `R15;
- assign flags_hazard = flags_dependency && updating_flags;
-
- assign updating_flags = final_update_flags || update_flags;
- assign flags_dependency = dec.psr.update_flags || dec.ctrl.conditional;
-
always_ff @(posedge clk or negedge rst_n)
bubble <= !rst_n ? 0 : next_cycle.issue && next_bubble;