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| author | Alejandro Soto <alejandro@34project.org> | 2022-11-07 19:07:55 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-07 19:07:55 -0600 |
| commit | 4ccb96c1aaf348f677954171751b58ad8f4dccf1 (patch) | |
| tree | 50fc326e176570a151b0270d02ea99bec737315f /rtl/core/control/select.sv | |
| parent | c67a1007045a9bf0282c26da74149723c6a2941d (diff) | |
Remove false dependencies on control.issue (long combinational)
Diffstat (limited to 'rtl/core/control/select.sv')
| -rw-r--r-- | rtl/core/control/select.sv | 14 |
1 files changed, 6 insertions, 8 deletions
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv index 3c0ec6c..62ad503 100644 --- a/rtl/core/control/select.sv +++ b/rtl/core/control/select.sv @@ -9,8 +9,7 @@ module core_control_select input ctrl_cycle cycle, next_cycle, - input logic issue, - mem_ready, + input logic mem_ready, pop_valid, input reg_num popped, final_rd, @@ -31,11 +30,10 @@ module core_control_select rb = last_rb; unique case(next_cycle) - ISSUE: - if(issue) begin - ra = dec_data.rn; - rb = dec_snd.r; - end + ISSUE: begin + ra = dec_data.rn; + rb = dec_snd.r; + end TRANSFER: if(cycle != TRANSFER || mem_ready) @@ -53,7 +51,7 @@ module core_control_select last_ra <= ra; last_rb <= rb; - if(next_cycle == ISSUE && issue) + if(next_cycle == ISSUE) r_shift <= dec_snd.r_shift; end |