diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-12-18 18:31:03 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-12-18 18:31:03 -0600 |
| commit | e290956adf94dade4c9c4cd057cca08af1c61aeb (patch) | |
| tree | df310fe32102781b48d20d66b5c51cfdb2ad7901 /rtl/core/control/select.sv | |
| parent | 46eae9622ab6f1a39c6253dc0998e03c57513510 (diff) | |
Implement privileged ldm/stm of user registers
Diffstat (limited to 'rtl/core/control/select.sv')
| -rw-r--r-- | rtl/core/control/select.sv | 29 |
1 files changed, 26 insertions, 3 deletions
diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv index 0ab7bb2..dc04282 100644 --- a/rtl/core/control/select.sv +++ b/rtl/core/control/select.sv @@ -8,7 +8,9 @@ module core_control_select input insn_decode dec, input ctrl_cycle next_cycle, - input logic mem_ready, + input psr_mode mode, + input logic issue, + mem_ready, pop_valid, ldst_next, input reg_num popped, @@ -17,11 +19,18 @@ module core_control_select mul_r_add_hi, output reg_num ra, - rb + rb, + output psr_mode rd_mode, + wr_mode, + output logic rd_user ); + logic wr_user; reg_num r_shift, last_ra, last_rb; + assign rd_mode = rd_user ? `MODE_USR : mode; + assign wr_mode = wr_user ? `MODE_USR : mode; + always_comb begin ra = last_ra; rb = last_rb; @@ -46,12 +55,26 @@ module core_control_select last_ra <= {$bits(ra){1'b0}}; last_rb <= {$bits(rb){1'b0}}; r_shift <= {$bits(r_shift){1'b0}}; + + rd_user <= 0; + wr_user <= 0; end else begin last_ra <= ra; last_rb <= rb; - if(next_cycle.issue) + if(rd_user && next_cycle.transfer) + wr_user <= 1; + + if(rd_user && !next_cycle.transfer) + rd_user <= 0; + + if(wr_user && !next_cycle.transfer) + wr_user <= 0; + + if(next_cycle.issue) begin r_shift <= dec.snd.r_shift; + rd_user <= issue && dec.ctrl.ldst && dec.ldst.user_regs; + end end endmodule |