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authorAlejandro Soto <alejandro@34project.org>2022-12-14 22:24:58 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-16 16:29:10 -0600
commitef151fffb14eac19a19121dfb4c1e015e7470038 (patch)
treed3fe7d47e26bbf83cf2d38986e5f823d4e5dbb98 /rtl/core/control/psr.sv
parentd2be560fa668cefcc5eff6b88180f12fec0c326e (diff)
Fix register corruption when interrupting a load-store
Diffstat (limited to 'rtl/core/control/psr.sv')
-rw-r--r--rtl/core/control/psr.sv1
1 files changed, 1 insertions, 0 deletions
diff --git a/rtl/core/control/psr.sv b/rtl/core/control/psr.sv
index 07bf4e5..ff9b13f 100644
--- a/rtl/core/control/psr.sv
+++ b/rtl/core/control/psr.sv
@@ -77,6 +77,7 @@ module core_control_psr
psr_wr_control <= 1;
exception_spsr <= cpsr_rd;
end else if(next_cycle.exception) begin
+ psr <= 0;
psr_saved <= 1;
psr_wr_flags <= 1;
end else if(next_cycle.psr)