diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-11-13 05:22:23 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-13 05:54:44 -0600 |
| commit | d463acba5f9589085afb3dcc4058d82908ff90f2 (patch) | |
| tree | e4ba47f2f9daa8e25b5c244f7af934ff18b54cbc /rtl/core/control/mul.sv | |
| parent | 6cb000adf57d7af2ec4aac8fd93d12f09cc63556 (diff) | |
Convert core state machines to Quartus-inferring RTL
Diffstat (limited to 'rtl/core/control/mul.sv')
| -rw-r--r-- | rtl/core/control/mul.sv | 31 |
1 files changed, 13 insertions, 18 deletions
diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv index 9e66053..8352435 100644 --- a/rtl/core/control/mul.sv +++ b/rtl/core/control/mul.sv @@ -47,24 +47,19 @@ module core_control_mul end else begin mul_start <= 0; - unique case(next_cycle) - ISSUE: begin - mul <= issue && dec.ctrl.mul; - mul_add <= dec.mul.add; - mul_long <= dec.mul.long_mul; - mul_signed <= dec.mul.signed_mul; - mul_r_add_hi <= dec.mul.r_add_hi; - mul_r_add_lo <= dec.mul.r_add_lo; - end - - MUL: - mul_start <= cycle != MUL; - - MUL_ACC_LD: begin - hold_a <= rd_value_a; - hold_b <= rd_value_b; - end - endcase + if(next_cycle.issue) begin + mul <= issue && dec.ctrl.mul; + mul_add <= dec.mul.add; + mul_long <= dec.mul.long_mul; + mul_signed <= dec.mul.signed_mul; + mul_r_add_hi <= dec.mul.r_add_hi; + mul_r_add_lo <= dec.mul.r_add_lo; + end else if(next_cycle.mul) + mul_start <= !cycle.mul; + else if(next_cycle.mul_acc_ld) begin + hold_a <= rd_value_a; + hold_b <= rd_value_b; + end end //TODO: mul update_flags |