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authorAlejandro Soto <alejandro@34project.org>2022-11-07 19:07:55 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-07 19:07:55 -0600
commit4ccb96c1aaf348f677954171751b58ad8f4dccf1 (patch)
tree50fc326e176570a151b0270d02ea99bec737315f /rtl/core/control/ldst
parentc67a1007045a9bf0282c26da74149723c6a2941d (diff)
Remove false dependencies on control.issue (long combinational)
Diffstat (limited to 'rtl/core/control/ldst')
-rw-r--r--rtl/core/control/ldst/ldst.sv21
1 files changed, 11 insertions, 10 deletions
diff --git a/rtl/core/control/ldst/ldst.sv b/rtl/core/control/ldst/ldst.sv
index 0a2f6c9..c8dac7c 100644
--- a/rtl/core/control/ldst/ldst.sv
+++ b/rtl/core/control/ldst/ldst.sv
@@ -46,18 +46,19 @@ module core_control_ldst
always_ff @(posedge clk)
unique case(next_cycle)
- ISSUE:
- if(issue) begin
- // TODO: dec_ldst.unprivileged/user_regs
- // TODO: byte/halfword sizes
+ ISSUE: begin
+ // TODO: dec_ldst.unprivileged/user_regs
+ // TODO: byte/halfword sizes
+ if(issue)
ldst <= dec.ldst;
- ldst_pre <= dec_ldst.pre_indexed;
- ldst_increment <= dec_ldst.increment;
- ldst_writeback <= dec_ldst.writeback;
- mem_regs <= dec_ldst.regs;
- mem_write <= !dec_ldst.load;
- end
+ ldst_pre <= dec_ldst.pre_indexed;
+ ldst_increment <= dec_ldst.increment;
+ ldst_writeback <= dec_ldst.writeback;
+
+ mem_regs <= dec_ldst.regs;
+ mem_write <= !dec_ldst.load;
+ end
TRANSFER: begin
if(cycle != TRANSFER) begin