Refactor decode signals into unified insn_decode struct

1 files changed, 14 insertions, 14 deletions

diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index 6ad27f7..5ed03f0 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -2,34 +2,34 @@
 
 module core_control_issue
 (
-	input  logic           clk,
+	input  logic       clk,
 
-	input  datapath_decode dec,
-	input  ptr             fetch_insn_pc,
+	input  insn_decode dec,
+	input  ptr         fetch_insn_pc,
 
-	input  ctrl_cycle      next_cycle,
-	input  logic           next_bubble,
+	input  ctrl_cycle  next_cycle,
+	input  logic       next_bubble,
 
 `ifdef VERILATOR
-	input  word            insn,
+	input  word        insn,
 `endif
 
-	output logic           issue,
-	                       undefined,
-	output ptr             pc,
-	                       pc_visible,
-	                       next_pc_visible
+	output logic       issue,
+	                   undefined,
+	output ptr         pc,
+	                   pc_visible,
+	                   next_pc_visible
 );
 
-	assign issue = next_cycle == ISSUE && dec.execute && !next_bubble;
+	assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble;
 	assign next_pc_visible = fetch_insn_pc + 2;
 
 	always_ff @(posedge clk)
 		if(next_cycle == ISSUE) begin
-			undefined <= dec.undefined;
+			undefined <= dec.ctrl.undefined;
 
 `ifdef VERILATOR
-			if(dec.undefined)
+			if(dec.ctrl.undefined)
 				$display("[core] undefined insn: [0x%08x] %08x", fetch_insn_pc << 2, insn);
 `endif