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authorAlejandro Soto <alejandro@34project.org>2022-12-11 23:54:38 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-16 16:29:10 -0600
commit79e05aa7f0ccce6eb26248ddef3e928727857a9c (patch)
tree8c67d6532234dac0eace7f005638efc8441105a5 /rtl/core/control/exception.sv
parent0284628a47d5b4797c89f6846b9efee3f1243b94 (diff)
Implement prefetch aborts
Diffstat (limited to '')
-rw-r--r--rtl/core/control/exception.sv6
1 files changed, 5 insertions, 1 deletions
diff --git a/rtl/core/control/exception.sv b/rtl/core/control/exception.sv
index 2d12c0a..038cd2b 100644
--- a/rtl/core/control/exception.sv
+++ b/rtl/core/control/exception.sv
@@ -8,6 +8,7 @@ module core_control_exception
input ctrl_cycle next_cycle,
input logic high_vectors,
undefined,
+ prefetch_abort,
mem_fault,
output logic exception,
@@ -20,7 +21,7 @@ module core_control_exception
//TODO: irq, fiq, prefetch abort, swi
- assign exception = undefined || mem_fault;
+ assign exception = undefined || prefetch_abort || mem_fault;
assign exception_vector = {{16{high_vectors}}, 11'b0, vector_offset, 2'b00};
always @(posedge clk or negedge rst_n) begin
@@ -31,6 +32,9 @@ module core_control_exception
end else if(mem_fault) begin
vector_offset <= 3'b100;
exception_mode <= `MODE_ABT;
+ end else if(prefetch_abort) begin
+ vector_offset <= 3'b011;
+ exception_mode <= `MODE_ABT;
end else if(undefined) begin
vector_offset <= 3'b001;
exception_mode <= `MODE_UND;