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authorAlejandro Soto <alejandro@34project.org>2022-11-10 10:11:33 -0600
committerAlejandro Soto <alejandro@34project.org>2022-11-10 10:11:33 -0600
commitacca3eb31a051f335c51306786bb972c21634998 (patch)
tree9f8fc3da1a8494e88c5043735862e56c54356bc0 /rtl/core/control/data.sv
parent0f89db514bd174def590645c30a7bd358ea6be93 (diff)
Fix reset glitches
Diffstat (limited to 'rtl/core/control/data.sv')
-rw-r--r--rtl/core/control/data.sv5
1 files changed, 3 insertions, 2 deletions
diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv
index fc936dc..0824eac 100644
--- a/rtl/core/control/data.sv
+++ b/rtl/core/control/data.sv
@@ -69,6 +69,7 @@ module core_control_data
c_in <= 0;
shifter <= {$bits(shifter){1'b0}};
data_imm <= {$bits(data_imm){1'b0}};
+ saved_base <= 0;
data_shift_imm <= {$bits(data_shift_imm){1'b0}};
data_snd_is_imm <= 0;
data_snd_shift_by_reg <= 0;
@@ -77,10 +78,10 @@ module core_control_data
alu <= dec.data.op;
c_in <= flags.c;
- data_snd_is_imm <= dec.snd.is_imm;
- data_snd_shift_by_reg <= dec.snd.shift_by_reg;
data_imm <= dec.snd.imm;
data_shift_imm <= dec.snd.shift_imm;
+ data_snd_is_imm <= dec.snd.is_imm;
+ data_snd_shift_by_reg <= dec.snd.shift_by_reg;
shifter.shr <= dec.snd.shr;
shifter.ror <= dec.snd.ror;