diff options
| author | Alejandro Soto <alejandro@34project.org> | 2022-10-31 16:05:15 -0600 |
|---|---|---|
| committer | Alejandro Soto <alejandro@34project.org> | 2022-11-01 23:04:24 -0600 |
| commit | 41b263bb39478393a302b284643a590779902f6c (patch) | |
| tree | 85a37c65c356aad3303e539228c3c770e166b907 /rtl/core/control/cycles.sv | |
| parent | b171ab92f6f7787ca483b83d4b34bbb97f167896 (diff) | |
Add MUL control cycle
Diffstat (limited to 'rtl/core/control/cycles.sv')
| -rw-r--r-- | rtl/core/control/cycles.sv | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/rtl/core/control/cycles.sv b/rtl/core/control/cycles.sv index f804e93..e9bc2da 100644 --- a/rtl/core/control/cycles.sv +++ b/rtl/core/control/cycles.sv @@ -3,10 +3,12 @@ module core_control_cycles ( input logic clk, + mul, ldst, bubble, exception, mem_ready, + mul_ready, pop_valid, trivial_shift, ldst_writeback, @@ -38,13 +40,21 @@ module core_control_cycles else if(ldst_writeback) next_cycle = BASE_WRITEBACK; + MUL: + if(!mul_ready) + next_cycle = MUL; + default: ; endcase if(bubble) next_cycle = ISSUE; - else if(next_cycle == ISSUE && ldst) - next_cycle = TRANSFER; + else if(next_cycle == ISSUE) begin + if(ldst) + next_cycle = TRANSFER; + else if(mul) + next_cycle = MUL; + end end always_ff @(posedge clk) |