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authorAlejandro Soto <alejandro@34project.org>2022-12-09 00:32:34 -0600
committerAlejandro Soto <alejandro@34project.org>2022-12-09 00:36:44 -0600
commitb2b2d5124db13714ed82181c9558568d908dfa2a (patch)
tree1779e0751eb49b1a62beff291792455a7e4ff740 /rtl/core/control/coproc.sv
parent2cbccf921bf84665c55cea67b81f31c66dde4249 (diff)
Implement cp15 control
Diffstat (limited to 'rtl/core/control/coproc.sv')
-rw-r--r--rtl/core/control/coproc.sv26
1 files changed, 18 insertions, 8 deletions
diff --git a/rtl/core/control/coproc.sv b/rtl/core/control/coproc.sv
index 76f0a53..05ac655 100644
--- a/rtl/core/control/coproc.sv
+++ b/rtl/core/control/coproc.sv
@@ -2,21 +2,31 @@
module core_control_coproc
(
- input logic clk,
- rst_n,
+ input logic clk,
+ rst_n,
- input insn_decode dec,
+ input insn_decode dec,
+ input word coproc_read,
- input ctrl_cycle next_cycle,
- input logic issue,
+ input ctrl_cycle next_cycle,
+ input logic issue,
- output logic coproc
+ output logic coproc,
+ output word coproc_wb,
+ output coproc_decode coproc_ctrl
);
always_ff @(posedge clk or negedge rst_n)
- if(!rst_n)
+ if(!rst_n) begin
coproc <= 0;
- else if(next_cycle.issue && issue)
+ coproc_wb <= 0;
+ coproc_ctrl <= {$bits(coproc_ctrl){1'b0}};
+ end else if(next_cycle.issue && issue) begin
coproc <= dec.ctrl.coproc;
+ coproc_ctrl <= dec.coproc;
+ end else if(next_cycle.coproc) begin
+ coproc <= 0;
+ coproc_wb <= coproc_read;
+ end
endmodule